[VHDL/FPGA/Verilog] acorn-electron-core
用于FPGA回放的橡果电子核心。
Acorn Electron core for the FPGA Replay. (2022-11-20, VHDL, 265KB, 下载0次)
[VHDL/FPGA/Verilog] Introduction-to-FPGA-Design-for-Embedded-Systems
我的活动出现在这里，版权归科罗拉多博尔德大学所有这是个人使用。
My activities appear here,Copyrights to Colorado Boulder University-This is for personal use. (2020-10-17, VHDL, 35133KB, 下载0次)
[VHDL/FPGA/Verilog] Hardware-Description-Languages-for-FPGA-Design
我的高密度脂蛋白活动出现在这里。这是我个人用的。PPT版权归科罗拉多大学博尔德分校所有。
My HDL activities appear here. This is for my personal use. PPT s copyrights to University of Colorado Boulder. (2020-10-17, VHDL, 51878KB, 下载0次)
[VHDL/FPGA/Verilog] Space_Invaders
博洛尼亚大学VHDL程序“72943-数字系统M”
Progetto VHDL sviluppato nell ambito del corso "72943 - Sistemi Digitali M" dell Università di Bologna (2015-05-27, VHDL, 106KB, 下载0次)
[VHDL/FPGA/Verilog] can_latest.tar
控制器局域网或CAN是一个控制网络协议
博世在工业自动化和工业自动化中得到了广泛的应用
汽车行业。
大多数的专利可以由博世拥有，虽然有
没有限制在开发一个开源IP但可以为任何
从博世商用许可协议是一个不可或缺的先决条件。
尺寸大约12K门（930触发器）。
Controller Area Network or CAN is a control network protocol
Bosch that has found wide use in Industrial Automation and the
Automotive Industry.
Most of the patents of CAN are owned by Bosch and although there
are no restictions on developing an opensource CAN IP but for any
commercial use the protocol license Bosch is an indispensable prerequisite.
Size is approximately 12k gates (930 flip-flops). (2017-02-16, VHDL, 1145KB, 下载2次)
[VHDL/FPGA/Verilog] xapp1052
Xilinx 关于PCIE读写控制的官方例程。
Xilinx PCIE Demo (2016-10-21, VHDL, 13345KB, 下载42次)
[VHDL/FPGA/Verilog] LED
用FPGA程序产生LED灯点亮，可以实现跑马灯，交通信号等效果
FPGA LED (2015-06-11, VHDL, 223KB, 下载1次)
[VHDL/FPGA/Verilog] music_ic
此為VHDL之音樂IC設計，透過Max Plus II將設計結果顯示。
This is the music of IC design VHDL, designed by Max Plus II results will be displayed. (2014-11-24, VHDL, 396KB, 下载1次)
[VHDL/FPGA/Verilog] Verilogbook
夏闻博书籍描述verilog语言开发，详细介绍语法的运用。经典收藏
Xia Wen Bo books describe verilog language development, detailing the use of grammar. Classic Collection (2013-11-07, VHDL, 1324KB, 下载2次)
[VHDL/FPGA/Verilog] 8929736539335
貪食蛇程式寫作，主要說明貪食蛇吃蘋果及上下左右移動
Snake program writing (2012-05-26, VHDL, 7KB, 下载7次)
[VHDL/FPGA/Verilog] miniprinter
微型打印机模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。
在quartusII里面添加uart核，nios II的Console构成人机交互界面，串口与微型打印机通信，打印出数据。
Micro printer module experiment rar core on the FPGA-2C35 Borch experimental box platform. QuartusII inside to add the uart nuclear, nios II Console constitute a man-machine interface, serial ports, and micro-printer communications, print out the data. (2012-05-18, VHDL, 12837KB, 下载8次)
[VHDL/FPGA/Verilog] BarcodeScan
条码扫描模块.rar；基于FPGA-2C35核心；博创实验箱平台。
串口设置：波特率57600bps,Parity: None Data:8 Stop:1
Bar code scanning module rar core Borch experimental box platform based on FPGA-2C35. Serial port settings: baud rate 57600bps, Parity: None Data: 8 Stop: 1 (2012-05-18, VHDL, 1360KB, 下载11次)
[VHDL/FPGA/Verilog] SensorBoard
多功能传感器模块实验.rar；基于FPGA-
2C35核心；博创实验箱平台。
Experiment of multi-functional sensor module. Rar core on the FPGA-2C35 Borch experimental box platform. (2012-05-18, VHDL, 12809KB, 下载11次)
[VHDL/FPGA/Verilog] paomadeng
跑马灯代码 阿斯好说的卡上接电话卡结舌杜口京哈蜀客多积货按时间dha空手道会卡水的空间has快结婚ask接电话
good VHDL code
asdhkashdkajshdkahskdjhaskjdhkash jkasdhkajsdh akjsdh ajkshd kajshd asjdh kajdh (2011-08-19, VHDL, 1KB, 下载2次)
[VHDL/FPGA/Verilog] UP-CUP-FPGA2C35-II
UP-CUP FPGA2C35-II平台使用说明书，用于博创嵌入式实验平台
UP-CUP FPGA2C35-II platform manual, embedded test platform for Borch (2011-08-07, VHDL, 4678KB, 下载6次)
[VHDL/FPGA/Verilog] div(FLP)
是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除
Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division (2009-03-17, VHDL, 18KB, 下载45次)
[VHDL/FPGA/Verilog] FIFO
用VERILOG写的FIFO程序，可以直接引用经本人测试
VERILOG written using FIFO procedures, can be directly invoked by the I test (2008-12-17, VHDL, 1099KB, 下载40次)
[VHDL/FPGA/Verilog] DE2_LCM_CCD_onchip.7z
將DE2連接到LCD版面上
內為友晶客科技公司所附製的程式碼
DE2 will connect to the LCD layout for Terasic off technology companies attached to the system code (2008-10-17, VHDL, 659KB, 下载50次)
[VHDL/FPGA/Verilog] verilog9
ｖｅｒｉｌｏｇ實現算術運算後利用7段顯示器將結果輸出
Verilog Arithmetic realize after the use of paragraph 7 displays the results output (2008-07-07, VHDL, 133KB, 下载3次)
[VHDL/FPGA/Verilog] lcd
设计实体：lcd驱动器
--彩色液晶芯片LQ080V3DG01
--原创针对博创开发板UP-SOPC2000开发板写的彩色液晶驱动程序
Design entities: lcd driver- Color LCD chip LQ080V3DG01- original development board for Fiberxon UP-SOPC2000 development board to write the color LCD driver (2008-06-12, VHDL, 1241KB, 下载89次)