[VHDL/FPGA/Verilog] SystemVerilog-for-Verification-Third-Edition-cn
SystemVerilog for Verification A Guide to Learning the Testbench Language Features Third Edition中文翻译,
SystemVerilog for Verification A Guide to Learning the Testbench Language Features Third Edition, (2022-01-10, Others, 0KB, 下载0次)
[VHDL/FPGA/Verilog] 开关电源设计第三版CN
高等学校电子信息类专业系列教材 EDA原理及Verilog HDL实现 从晶体管、门电路到Xilinx Vivado的数字系统设计_14149516
EDA Principle and Verilog HDL realization from transistor, gate circuit to Xilinx Vivado digital system design _14149516 (2020-12-07, Others, 58789KB, 下载1次)
[VHDL/FPGA/Verilog] eetop.cn_DDR_PHY_Interface_Specification_v4_0
具体讲的ddr phy的spec 资料，是学习的不错的参考
DDR phy introdcution (2019-12-25, Others, 1419KB, 下载6次)
[VHDL/FPGA/Verilog] eetop.cn_ASIC可测试性设计技术
生快生快到凌晨八块v京东快递快递是比较阿卡不行就先开始吧
dhknc shdkkssjdkfshsklckfsbhaja (2018-06-20, Others, 784KB, 下载0次)
[VHDL/FPGA/Verilog] Code-speed-adjustment-circuit
基于同步的数字 复接系统, 即输入的数据码流速率相同。若各 支路 的数 据码 流速 率不 同, 则 不能 直接 进行 复接, 因为复接合成后的数字信 号流, 在 接收端是无法分接恢复成原来的信号的, 为此在复接 前要使各支路数码率同步, 我们可以在设计的同步数字复接系 统前方加一码速调整单元, 以调整各支路的速码率使其同步, 并在分接 后再经过码速调整恢复为原来的速率。
Based on the synchronous digital multiplex system, namely the input data stream rate is the same. If the number of each branch, according to the code flow rate is not directly to pick up, because after the multiplex synthesis of digital signal flow, at the receiving end is unable to connect back to the original signal, so to make the selection in front of the multiplex synchronous digital rate, we can in the design of synchronous digital multiplex system System with a yard in front speed adjustment unit to adjust the selection of speed rate, synchronization and after yards after tapping speed adjust to restore to the original rate. (2015-12-30, Others, 681KB, 下载5次)
[VHDL/FPGA/Verilog] jk_ff
IT IS A VERILOG CODE FOR JK_FF.
IT IS A VERILOG CODE FOR JK_FF. (2015-09-23, Others, 155KB, 下载1次)
[VHDL/FPGA/Verilog] QII_Intro_CN
FPGA的入门教程，每一个都有说明，按照说明仔细的练习可以很快掌握FPGA
FPGA introductory tutorial, each with a description, follow the instructions carefully exercises can quickly grasp the FPGA (2013-10-09, Others, 22965KB, 下载3次)
[VHDL/FPGA/Verilog] Verilog-UART
功能：UART串口通讯实信实验
描述：本程序共四个模块
模块1：接收数据的波特率发生模块，接收模块在接收到下降沿时，通过标志位启
动该模块的波特率计数器，并在计数中返回一个采样标志位给接受模块，
通知接收模块采样；
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模块2：数据接收模块，该模块一旦监测到数据输入端有下降沿，就立即启动波
特率（标志位置1），并使能接收标志位rx_int，接收开始；
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模块3：发送数据的波特率发生模块，发送模块在监测到接收标志位rx_int产生下
降沿时，通过标志位启动该模块的的波特率计数器，并在计数中返回一
个发送标志位给发送模块，通知发送模块发送数据；
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模块4：数据发送模块，该模块一旦监测到接收标志位rx_int有下降沿，就立即启
动波特率（标志位置1），并使能接收标志位tx_en，发送开始；
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Verilog UART (2013-04-25, Others, 16KB, 下载25次)
[VHDL/FPGA/Verilog] src_gen
使用VHDL语言产生m序列，用于通信系统的随机信源
To generate m sequence with HHDL,whcih is used as random source in communication system (2012-09-14, Others, 1KB, 下载4次)
[VHDL/FPGA/Verilog] eetop.cn_FPGA-Design
飞利浦出的英文版的fpga设计，英文好的可以看看。
The Philips out the English version of the fpga design, English can look good. (2012-09-03, Others, 3346KB, 下载6次)
[VHDL/FPGA/Verilog] PWM256
Verilog 所寫的可程式 PWM 信號產生器. 特點是設定參數時不會產生Glitch現象. 包含二個 .do 檔給 model*sim 幫助編譯及模擬.
A PWM generator writing in Verilog. This module will generate glitch while changing the setting. Including 2 .do files which can help compiling and simulating in the model_sim. (2011-04-18, Others, 2KB, 下载17次)
[VHDL/FPGA/Verilog] dds-design
fpga实现dds，实现任意波形输出信，设计代码verilog
dds fpga realization (2010-12-21, Others, 1KB, 下载24次)
[VHDL/FPGA/Verilog] cn
Multiprogramming winder river
Multiprogramming winder river (2010-12-16, Others, 24871KB, 下载1次)
[VHDL/FPGA/Verilog] 74LS04_cn
74hc04中文资料。。。。。。。。。。。。。。。。。。。。
74hc04 Chinese data. . . . . . . . . . . . . . . . . . . . (2010-08-19, Others, 75KB, 下载5次)
[VHDL/FPGA/Verilog] CDC-Protocal(cn)
汽车音响CD机通讯控制协议CDC协议中文版。
CDC PROTOCAL (2010-06-04, Others, 235KB, 下载65次)
[VHDL/FPGA/Verilog] ML506_photo
XILINX ML506 开发板高清晰照片，用于学习virtex-5.
The photo of xilix ML506 board,there are high clear,using for learning VIETEX-5. (2009-12-11, Others, 3169KB, 下载42次)
[VHDL/FPGA/Verilog] up_261128143F5F01A9
为解决直接序列扩频系统的数字收发机中初始频率的捕获问题，提出了一种通过DFT变换，在频域
上进行抛物插值运算的频偏估计的算法。该算法可适应低信噪比、宽频率偏移范围的恶劣通信环境和突发的通信
模式，且算法复杂度较低。该算法已在FPGA 中实现。
To address the direct sequence spread spectrum system, the number of transceivers in the initial frequency of the capture problem, a transformation through the DFT, in the frequency domain for parabolic interpolation computing frequency offset estimation algorithms. The algorithm can be adapted to low signal to noise ratio, broadband rates offset the scope of bad communications environment and unexpected modes of communication, and the algorithm complexity low. The algorithm has been realized in the FPGA. (2007-12-01, Others, 62KB, 下载85次)
[VHDL/FPGA/Verilog] SYSTEMVIEW_FPGA
真序扩频通信系统的SYSTEMVIEW信真及其FPGA实现发送端设计
True sequence spread spectrum communication system SYSTEMVIEW letter really realize the sending end and FPGA design (2007-09-21, Others, 1465KB, 下载32次)
[VHDL/FPGA/Verilog] altera_avalon_i2c_slave_new
i2c从设备的源码，VHDL语言写的，有疑问请eMail：feng_er_cn@163.com
i2c-source from the equipment, VHDL language, and have questions, please eMail: feng_er_cn@163.com (2007-09-07, Others, 17KB, 下载237次)
[VHDL/FPGA/Verilog] calculator
用VHDL编写的计算器，能实现简单的加减乘除四则运算 (2007-08-28, Others, 21KB, 下载108次)
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