信號之值大部分跟狀態暫存器有關，所以當狀態暫存器改變一段時間後才能獲得，稱之為Ctrl_delay。另外指令解碼需要幾層之邏輯電路，因此延遲時間較長，稱為Dec_delay。
Most of the value of the signal with the state of the registers, when changing the state of registers after a certain period of time can be called Ctrl_delay. In addition the need for layers of instruction decode logic circuit, so the delay time is longer, as Dec_delay. (2009-07-10, VHDL, 170KB, 下载1次)