Example3 加/减法计数器
本例程实现的是一个加/减8 进制计数器。其中包括时钟输入、使能信号、加减控制信
号、复位信号、三位输入和一位进位位。
Example3 add/subtract counter implementation of this routine is a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit. (2009-08-26, VHDL, 25KB, 下载27次)
.net 3。2 企业级分布式项目案例，应用wcf技术
. net 3. 2 enterprise-class distributed project case, the application WCF technology (2008-05-14, VHDL, 7120KB, 下载139次)