[VHDL/FPGA/Verilog] an484_CN
用MAX II CPLD，通过SMBus 实现GPIO 引脚扩展
With the MAX II CPLD, achieved through the SMBus pin GPIO expansion (2010-01-17, MultiPlatform, 220KB, 下载4次)
[VHDL/FPGA/Verilog] Ethernet_verilog_ip_core
Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核，对学习verilog语言和以太网有很大帮助。
Ethernet (Ethernet) verilog ip core language used verilogHDL Ethernet soft-core, learning Verilog language and Ethernet are very helpful. (2008-03-18, MultiPlatform, 882KB, 下载634次)
[VHDL/FPGA/Verilog] SCH_RTL8019
RTL8019 10M 以太网芯片的参考使用电路.与FPGA直接连接进行控制.
RTL8019 10M Ethernet chip reference circuit. FPGA directly connected with the control. (2008-03-15, MultiPlatform, 27KB, 下载75次)
[VHDL/FPGA/Verilog] RedLogic_8019
使用RTL8019芯片进行以太网通讯的VERILOG源代码.
RTL8019 Ethernet chip to use the Verilog source code for communications. (2008-03-15, MultiPlatform, 15121KB, 下载52次)
[VHDL/FPGA/Verilog] ETHERNET
具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述
With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog description (2008-03-04, MultiPlatform, 68KB, 下载723次)
[VHDL/FPGA/Verilog] modelsim_guide_cn
modelsim操作指导
很适合入门
有实例
modelsim operation guidance is very suitable example of a portal (2007-06-09, MultiPlatform, 334KB, 下载223次)
[VHDL/FPGA/Verilog] wave_gen
波形发生器，带TESTBENCH，
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn (2006-08-19, MultiPlatform, 1KB, 下载37次)
[VHDL/FPGA/Verilog] BoothMultiplier
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn (2006-08-19, MultiPlatform, 2KB, 下载75次)
[VHDL/FPGA/Verilog] FSM02
异步复位状态机
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
asynchronous reset state machine-- State Machine with Asynchronou 's Reset-- dowload from : www.fpga.com.cn (2006-08-19, MultiPlatform, 1KB, 下载8次)
[VHDL/FPGA/Verilog] mo0re_FSM
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
-- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn (2006-08-19, MultiPlatform, 1KB, 下载8次)
[VHDL/FPGA/Verilog] decode_for_m68008
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
-- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn (2006-08-19, MultiPlatform, 1KB, 下载5次)
[VHDL/FPGA/Verilog] fifo_01
8位相等比较器，比较8位数是否相等
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
-- download from www.pld.com.cn & www.fpga.com.cn
eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn (2006-08-19, MultiPlatform, 1KB, 下载13次)
[VHDL/FPGA/Verilog] dsfs
扫描信号从C3 ～C0送入,信号依序为1000 ->0100 ->0010 -> 0001->1000 循环,当扫描信号为1000时,则扫描第0行中的四个按键. 扫描信号为0100时,则扫描第1行中的四个按键, 以此类推.如果有按键被按下,则R3～R0的输出信号中会有一个为1,但我们还是是无法确定哪一个键被按下,必須要从R3 ～R0 的输出信号与C3～C0的
scan signal from C0 to C3 into the signal in order of 1000-gt; 0100- gt; 0010- gt; 0001- gt; 1000 cycle, when the scanning signal to 1000, then scanning 0 line of four keys. Scanning signal for 0100, then scanning resolution a line of four buttons, and so on. if a button is pressed, R3 ~ R0 the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 ~ R0 with the output signal of C0 to C3 (2005-09-11, MultiPlatform, 110KB, 下载6次)
[VHDL/FPGA/Verilog] trans4_16
看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来
saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks (2005-08-13, MultiPlatform, 93KB, 下载9次)