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[VHDL/FPGA/Verilog] MyWay

使用yandex地图绘制白俄罗斯历史文化名胜路线的信息资源，
Information resource on drawing up routes to historical and cultural places of Belarus using yandex maps, (2023-08-29, HTML, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694143161228894.html

[VHDL/FPGA/Verilog] fpga_full_adder

FPGA实现全加器
FPGA implementation of full adder (2021-03-15, HTML, 906KB, 下载0次)

http://www.pudn.com/Download/item/id/1615765766355750.html

[VHDL/FPGA/Verilog] UART_fpga

普拉蒂加巴斯3
Práctica Basys 3 (2022-04-05, HTML, 54KB, 下载0次)

http://www.pudn.com/Download/item/id/1649097801354095.html

[VHDL/FPGA/Verilog] FPGA-Ping-Pong-game

赛灵思斯巴达3E上的简单乒乓球游戏
Simple Ping Pong game on Xilinx Spartan 3E (2022-04-29, HTML, 7910KB, 下载0次)

http://www.pudn.com/Download/item/id/1651185012765838.html

[VHDL/FPGA/Verilog] Tetris

俄罗斯方块通过用VHDL编程FPGA重新制作，显示在64x32 LED矩阵上。
Tetris remade by programming an FPGA in VHDL, to be displayed on a 64x32 LED matrix. (2019-09-24, HTML, 1543KB, 下载0次)

http://www.pudn.com/Download/item/id/1569265285659144.html

[VHDL/FPGA/Verilog] vhdl-asteroid-dodger

用vhdl为斯巴达3 FPGA板制作的游戏
A game made made with vhdl for the SPARTAN 3 FPGA board (2019-10-23, HTML, 1566KB, 下载0次)

http://www.pudn.com/Download/item/id/1571785834242909.html

[VHDL/FPGA/Verilog] vhdl-stopwatch

基于hdl的斯巴达板简易秒表
simple stopwatch using hdl for spartan board (2018-06-18, HTML, 302KB, 下载0次)

http://www.pudn.com/Download/item/id/1529255609815068.html

[VHDL/FPGA/Verilog] tetris-fpga-vhdl

俄罗斯方块fpga vhdl，，
tetris-fpga-vhdl,, (2019-03-31, HTML, 8739KB, 下载0次)

http://www.pudn.com/Download/item/id/1554038723911338.html

[VHDL/FPGA/Verilog] CISC530-ComputerSystemArchitecture

此存储库包含哈里斯堡大学计算机系统架构课程的硬件和作业
This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University (2019-11-18, HTML, 19576KB, 下载0次)

http://www.pudn.com/Download/item/id/1574069337553977.html

[VHDL/FPGA/Verilog] 丁哲琴201701130704董红芳201824101404

就是一个用maxplus2做的4位全加器啦
It's a four bit full adder made of maxplus 2 (2020-07-02, HTML, 178KB, 下载0次)

http://www.pudn.com/Download/item/id/1593659024792250.html

[VHDL/FPGA/Verilog] Design-of-full-adder

熟悉VHDL元件例化语句的作用熟悉全加器的工作原理用VHDL语言设计一位二进制全加器，并仿真。
The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation. (2015-03-10, HTML, 9KB, 下载2次)

http://www.pudn.com/Download/item/id/1425998909887566.html