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[硬件设计] Advanced-VLSI-Design

ECSE-6680项目：伦斯勒理工学院张彤教授的高级VLSI设计
Projects for ECSE-6680: Advanced VLSI Design with Professor Tong Zhang at Rensselaer Polytechnic Institute (2024-03-15, SystemVerilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1710539055773738.html

[硬件设计] Fulladder-UVM-verification

基于UVM的全加器（1位加法器）电路验证测试台。，
UVM based testbench for verification of Full adder (1-bit adder) circuit ., (2023-09-29, SystemVerilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1696018038331704.html

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