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[VHDL/FPGA/Verilog] iverilog-api

伊维里洛api
iverilog api (2024-01-24, Others, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1706156828630665.html

[VHDL/FPGA/Verilog] VERILOG

维罗格，，
VERILOG,, (2023-08-12, Others, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1691812876937048.html

[VHDL/FPGA/Verilog] P4-NetFPGA-public

P4 NetFPGA维基
P4-NetFPGA wiki (2018-02-26, Others, 70405KB, 下载0次)

http://www.pudn.com/Download/item/id/1519641391781319.html

[VHDL/FPGA/Verilog] 一位全加器的设计

全加器等等传输管简易模型，用于传输管的异或运算出来得全加器
A simple model of full adder and other transfer tubes (2018-11-15, Others, 425KB, 下载0次)

http://www.pudn.com/Download/item/id/1542290374284792.html

[VHDL/FPGA/Verilog] Butterworth

巴特沃斯带阻滤波器，能够很好的过滤掉高频信号，并且程序简单。
Butterworth band-stop filter, to filter out high frequency signal, and the program is simple. (2012-09-19, Others, 1KB, 下载13次)

http://www.pudn.com/Download/item/id/1996697.html

[VHDL/FPGA/Verilog] DF2C8_01_LED

led 灯的显示，加胆码整体功能。LED deng
led display (2011-12-11, Others, 328KB, 下载3次)

http://www.pudn.com/Download/item/id/1727475.html

[VHDL/FPGA/Verilog] verilog

曼彻斯特编码的verilog实现,复制到quartus II可用
Manchester verilog realize the code,Copy to quartus II available (2011-11-24, Others, 10KB, 下载84次)

http://www.pudn.com/Download/item/id/1709010.html

[VHDL/FPGA/Verilog] jiafaqi

实现一位全加器的运算，并通过调用模块实现四位全加器的运算
Implement a full adder operation, and by calling the module' s operation four full adder (2011-07-21, Others, 174KB, 下载10次)

http://www.pudn.com/Download/item/id/1603095.html

[VHDL/FPGA/Verilog] alu

本程序实现算术逻辑单元（ALU）设计，包括：清零、逻辑乘、逻辑加、异或、算术加、左移、右移等等功能。
Arithmetic logic unit to achieve the program design, including: clear, logical multiplication, logical add, XOR, arithmetic plus, left, right, and so function (2011-07-21, Others, 78KB, 下载6次)

http://www.pudn.com/Download/item/id/1603088.html

[VHDL/FPGA/Verilog] vga_game

用Verilog写的小游戏，俄罗斯方块,在VGA上实现游戏功能
Verilog game (2010-08-23, Others, 8483KB, 下载488次)

http://www.pudn.com/Download/item/id/1277263.html

[VHDL/FPGA/Verilog] Manchester

基于FPGA/CPLD，采用VHDL语言的曼彻斯特的编解码实现。还包含曼彻斯特码的说明文档。
Based on FPGA/CPLD, using VHDL language codec Manchester realize. Manchester code also includes documentation. (2008-03-08, Others, 171KB, 下载272次)

http://www.pudn.com/Download/item/id/412670.html

[VHDL/FPGA/Verilog] fulladder

全加器,有半加器和或门组成.元件例化语句.
Full adder, half adder and OR gate components. Components of sentence cases. (2008-01-09, Others, 12KB, 下载4次)

http://www.pudn.com/Download/item/id/390970.html

[VHDL/FPGA/Verilog] VHDL

自编自写的ＶＨＤＬ代码，用于实现全加器功能，可能有误
, Directed and written in VHDL code, for the realization of full-adder function, may have mistaken (2007-12-24, Others, 4KB, 下载4次)

http://www.pudn.com/Download/item/id/381665.html

[VHDL/FPGA/Verilog] myproject

四位全加器，VHDL语言，max+plusII平台做的
Four full-adder, VHDL language, max+ PlusII platform to do (2007-12-02, Others, 55KB, 下载11次)

http://www.pudn.com/Download/item/id/368554.html

[VHDL/FPGA/Verilog] adder4

verilog加法器,附加测试文件可用modelsim 仿真实现
Verilog Adder, additional test file ModelSim simulation can be used to achieve (2007-12-01, Others, 5KB, 下载359次)

http://www.pudn.com/Download/item/id/368270.html

[VHDL/FPGA/Verilog] add_1p

2级流水线实现的8位全加器的VHDL代码，适用于altera系列的FPGA/CPLD
Realize two lines of eight full adder of the VHDL code, applicable to altera series of FPGA/CPLD (2007-11-01, Others, 1KB, 下载7次)

http://www.pudn.com/Download/item/id/354105.html

[VHDL/FPGA/Verilog] manchesterdecoder

曼彻斯特解码程序，用VHDL语言编写，和编码程序配套使用
Manchester decoding procedures, using VHDL language, and coding procedures for supporting the use of (2007-10-10, Others, 1KB, 下载53次)

http://www.pudn.com/Download/item/id/343346.html

[VHDL/FPGA/Verilog] multi4

fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器
fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier (2007-02-28, Others, 1KB, 下载23次)

http://www.pudn.com/Download/item/id/251301.html

[VHDL/FPGA/Verilog] man_Verilog

曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了
Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use (2006-10-11, Others, 9KB, 下载79次)

http://www.pudn.com/Download/item/id/218027.html

[VHDL/FPGA/Verilog] add_sub_lab2

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。
experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting. (2006-08-13, Others, 59KB, 下载75次)

http://www.pudn.com/Download/item/id/209117.html