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[VHDL/FPGA/Verilog] 11

verilog 任意维矩阵求逆的verilog实现方式
Verilog arbitrary-dimensional matrix inversion methods to achieve the Verilog (2008-11-06, MultiPlatform, 198KB, 下载357次)

http://www.pudn.com/Download/item/id/574181.html

[VHDL/FPGA/Verilog] manchesterforvhdl

这是一个曼彻斯特编解码的VHDL源代码，非常好，值得一看。
Manchester codec VHDL source code, a very good eye-catcher. (2006-05-06, MultiPlatform, 10KB, 下载76次)

http://www.pudn.com/Download/item/id/180717.html

[VHDL/FPGA/Verilog] Full_Adder

全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼
full adder and the VHDL_CODE TEST_BENCH not extract passwords (2006-04-06, MultiPlatform, 1KB, 下载6次)

http://www.pudn.com/Download/item/id/166927.html

[VHDL/FPGA/Verilog] Booth_Multiplier

布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.
Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can. (2006-04-06, MultiPlatform, 1KB, 下载72次)

http://www.pudn.com/Download/item/id/166785.html

[VHDL/FPGA/Verilog] 曼彻斯特编解码 Xilinx提供_vhdl

曼彻斯特编解码 Xilinx提供的VHDL的源代码
Manchester codec Xilinx provide VHDL source code (2005-10-24, MultiPlatform, 10KB, 下载108次)

http://www.pudn.com/Download/item/id/119610.html

[VHDL/FPGA/Verilog] 8位相位相加乘法器

8位相加乘法器，具有高速，占用资源较少的优点
eight multiplier phase together with high-speed, taking up less resources advantages (2005-08-09, MultiPlatform, 4KB, 下载57次)

http://www.pudn.com/Download/item/id/106664.html

总计:6