本文首先分析了目前常用的硬盘数据加密方法，并在比较各种加密方案的基础上给出了基于FPGA的加解密SATA IP设计方案。本文介绍设计SATA IP相关的基础知识，包括SATA的体系结构。本sata IP已在Xilinx spartan-6系列上实现并产品化，具有低成本优势，且可以根据用户意愿更换加密算法和使用私有的加密算法。本文还论述了加密SATA IP的各种应用前景。
This paper firstly analyzes several common ways of Hard Disk data protection, and then presents the design scheme of Encryption/Decryption SATA IP based on FPGA after comparison. Because of the common use of SATA2.0 interface, this paper then introduces the system structure of SATA2.0 protocol. The sata IP has been achieved and the products on the Xilinx spartan-6 series, they has low cost advantage. This article also discusses the outlook for a variety of applications to encrypt SATA IP s. (2014-04-23, PDF, 1895KB, 下载33次)
具有加、减计数以及置数报警功能的计数器，采用三个数码管显示，555产生1秒的脉冲，三块74ls192十进制计数器级联为三位数计数器。
Have add, subtract count, and buy several alarm function of counter, using three digital pipe display, 555 produce 1 second pulse, three pieces of 74 ls192 decimal counter level three digits backed counter. (2011-12-07, PDF, 81KB, 下载6次)
现场可编程门阵列（FPGA）是目前应用非常广泛的一种专用集成电路。在FPGA平台上实现了2位全加器硬宏的设计
Field programmable gate array (FPGA) is widely used as a specific integrated circuit. The FPGA platform for a two full adder hard macro design (2011-07-13, PDF, 750KB, 下载6次)
信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。
FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems. (2008-12-21, PDF, 301KB, 下载18次)
verilog语言中 testbencch编写-仿真工具综合工具使用-全加器实例讲解
Verilog language testbencch preparation- the use of simulation tools integrated tools- examples of full adder on the (2008-01-11, PDF, 185KB, 下载8次)
VHDL 开发PCI加密解密卡
逢甲大學
資訊工程學系專題報告
PCI 介面之加解密卡製作
VHDL development of PCI card encryption and decryption of information the Department of Engineering, Feng Chia University special report PCI interface card making encryption and decryption (2007-10-23, PDF, 411KB, 下载92次)