synplify中tcl语言应用，使用AdderE八位全加器为例，介绍一个设计针对不同器件综合
synplify in the tcl language application, use AdderE eight full-adder as an example, an integrated design for different devices (2009-11-09, TEXT, 1KB, 下载17次)
数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。
data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference. (2005-12-11, TEXT, 11KB, 下载236次)