基于VHDL的硬件乘加器设计,包括QUARTERS 的文件以及实验报告,便于参考和修改
Hardware multiplier design based on VHDL, including the QUARTERS file as well as the experimental report, ease of reference and modification (2015-12-20, WORD, 943KB, 下载1次)
EDA实验
实验实现从0-9，10个计数值在阴极LED数码管1-6上每次加1的同时循环左移显示。
实验实现在阴极LED数码管上1，2上动态显示0-99计数。
EDA experiment experimental increments to achieve from 0-9,10 one count value on the cathode LED digital tube 1-6 1 Rotate Left display. The experimental realization of the 1,2 cathode LED digital tube dynamic display 0-99 count. (2013-02-26, WORD, 48KB, 下载3次)
实验一 1位全加器的设计 详细的试验步骤一节过程分析！
Experiment-1 adder design a detailed process analysis of test steps! (2010-04-23, WORD, 827KB, 下载3次)
基于eda中vhdl语言的一位全加器的设计，详细的设计过程和实验现象，相互学习
Based on EDA VHDL language in a full adder design, detailed design process and the experimental phenomena and learn from each other (2008-11-20, WORD, 839KB, 下载4次)
利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计，不但具有较高的测量精度，而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量，在前端输入加整形电路即可。
use ultra-high-speed Hardware Description Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be. (2007-05-19, WORD, 30KB, 下载149次)
4位全加器原码，包括仿真码和4位计数器码。
four full adder original code, including the simulation code and four counter code. (2007-04-14, WORD, 3KB, 下载12次)
曼彻斯特编解码~VHDL?顾固乇嘟饴雫VHDL曼彻斯特编解码~VHDL
Manchester codec ~ VHDL Manchester codec VHDL Manchester ~ ~ VHDL codec Manchester codec ~ VHDL (2006-06-10, WORD, 10KB, 下载16次)
此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。
this procedure code decoder VHDL hardware is used to prepare the language. (2005-09-24, WORD, 3KB, 下载87次)