模拟CMOS电路设计，国外经典教程，拉扎维著
Design Of Analog CMOS Integarted Circuits (2012-09-25, VHDL, 16067KB, 下载4次)
m序列产生，汉明编码，人工加错，自动纠错，译码。m序列和汉明码采用不同时钟。
m sequence generation, Hamming codes, artificial a mistake, automatic error correction, decoding. m sequences and hamming different clock. (2011-05-07, VHDL, 1KB, 下载10次)
要求设计一个带闹钟功能的24小时计时器
它包括以下几个组成部分：
① 显示屏：4个七段数码管显示当前时间(时：分)或设置的闹钟时间；一个发光二极管以1HZ的频率跳动，用于显示秒；
② 按键key1，用于设置调时还是调分；
③ 按键key2，用于输入新的时间或新的闹钟时间，每按下一次，时或分加1；
④ TIME(时间)键，用于确定新的时间设置；
⑤ ALARM(闹钟)键，用于确定新的闹钟时间设置，或显示已设置的闹钟时间；
⑥ 扬声器，在当前时钟时间与闹钟时间相同时，发出蜂鸣声。
To design a 24-hour alarm clock with a timer which includes the following components: ① Display: 4 segment digital tube displays the current time (hours: minutes) or set the alarm time a light-emitting diode to the frequency of 1HZ beating, is used to display seconds ② keys key1, when used to set the tone or the tone pm ③ key key2, used to enter the new time or a new alarm time, every time you press, or points plus 1 ④ TIME ( time) key, used to determine the new time settings ⑤ ALARM (alarm) button, used to determine a new set alarm time, or set the alarm time is displayed ⑥ Speaker, in the current time and alarm clock the same time, issue beep. (2011-03-02, VHDL, 253KB, 下载12次)
l、设计用于竞赛的四人抢答器，功能如下：
(1) 有多路抢答器，台数为四；
(2) 具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警；
(3) 能显示超前抢答台号并显示犯规警报；
(4) 能显示各路得分，并具有加、减分功能；
2、系统复位后进入抢答状态，当有一路抢答键按下时，该路抢答信号将其余各路抢答封锁，同时铃声响，直至该路按键松开，显示牌显示该路抢答台号。
3、用VHDL语言设计符合上述功能要求的四人抢答器，并用层次设计方法设计该电路
l, designed for Answer four contests, and features are as follows: (1) Answer the way how, and the number to four (2) Answer 20 seconds after the beginning of the countdown, countdown to 20 seconds after the Answer shows no overtime, and report to the police (3) can show in advance Answer Desk No. foul alarm and display (4) can display various scoring with Canada, by sub-function 2, the system reset after entering the Answer state, all the way when pressing the Answer key , the signals will be the rest of the way each Answer Answer blockade, ring tones at the same time, release the button until the road, the road signs showing the number Answer Desk. 3, using VHDL language design meets the functional requirements of the above Answer four devices, and design method-level design of the circuit (2008-12-19, VHDL, 298KB, 下载125次)