[驱动编程] 1-D-Time-Domain-Convolution-on-FPGA

在本项目中，FPGA被编程为使用VHDL执行一维时域卷积。它由两个主要部分组成，将由......、...，
In this project a FPGA is programmed to perform 1-D time domain convolution using VHDL. It consists of two major parts to be completed which were the DMA interface between memory(DRAM) and the user_app and the design oof the signal and kernel buffers to perform convolution. (2022-02-11, VHDL, 0KB, 下载0次)