为Zybo FPGA设计的操纵杆控制俄罗斯方块游戏。
A joystick-controlled Tetris game designed for a Zybo FPGA. (2021-03-31, VHDL, 99KB, 下载0次)
用verilog语言开发俄罗斯方块小游戏
Developing Tetris game with Verilog language (2020-11-27, VHDL, 46721KB, 下载2次)
利用红外线控制方块上下移动的俄罗斯方块游戏。
Use infrared to move up and down. (2018-04-20, VHDL, 6278KB, 下载1次)
贪吃蛇游戏机
用一个 8×8 点阵做为基本显示屏，4 个连续移动的的发光点表示一条蛇，用任意出现的一个亮点表示老鼠，用4 个排成一条线的发光点表示“墙”；用两位拨码开关控制蛇的运动方向，蛇撞“墙”、边或者游戏时间到，则游戏结束；老鼠出现的位置是随机的，每次出现的时间是5 秒钟，如果5 秒钟之内没有被吃掉，它就会在其它地方出现；用数码管显示得分情况和游戏剩余时间，每吃掉一次老鼠就加一分。
Snake game console with a 88 dot matrix display as a basic, four consecutive moves luminous dots represent a snake, with any appearance of a bright spot, said the mouse, with four arranged in a line of luminous dots " wall" with two DIP switches control the direction of movement of the snake, the snake hit the " wall" , side or until game time, the game is over the position of the mouse appears to be random, time is 5 seconds for each occurrence, if not eaten within five seconds, it will appear in other places with digital display scores and game time remaining, every time a mouse eat plus one point. (2014-12-21, VHDL, 2KB, 下载6次)
拔河游戏机， 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15个(或9个)发光二极管，开机后只有中间一个发亮，此即拔河的中心点。 3、 游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。 4、 亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。 5、 用数码管显示获胜者的盘数。 教学提示: 1、 按钮信号即输入的脉冲信号，每按一次按钮都应能进行有效的计数。 2、 用可逆计数器的加、减计数输入端分别接受两路脉冲信号，可逆计数器原始输出状态为0000，经译码器输出，使中间一只二极管发亮。 3、 当计数器进行加法计数时，亮点向右移；进行减法计数时，亮点向左移。 4、 由一个控制电路指示谁胜谁负，当亮点移到任一方终端时，由控制电路产生一个信号，使计数器停止计数。 5、 将双方终端二极管“点亮”信号分别接两个计数器的“使能”端，当一方取胜时，相应的计数器进行一次计数，这样得到双方取胜次数的显示。 6、 设置一个“复位”按钮，使亮点回到中心，取胜计数器也要设置一个“复位”按钮，使之能清零。
1, the design of a circuit can be a tug of war game. 2, the circuit using the 15 (or 9) light-emitting diodes, after only among a shiny, namely the center of a tug of war. 3, the game with a two button rapidly and continuously pressed, generates a pulse, who by fast, highlight moves to whom the direction each time, the highlight moves once. 4, the highlight moves to either terminal diode, this party would win, this time the two sides button had no effect, the output remains only reset after making the highlight back to the center. 5, with digital display plate number winner. Teaching tips: 1, the signal that is input pulse signal button, each press of the button should be able to effectively counter. 2, with a reversible counter, plus or minus count input pulse signal, respectively, to receive two-way, reversible counter status for the 0000 original output by the decoder output, so that the middle one diode lights up. 3, when the counter counts up, the highlight to the right When subt (2014-06-18, VHDL, 443KB, 下载14次)
拔河游戏机， 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15个(或9个)发光二极管，开机后只有中间一个发亮，此即拔河的中心点。 3、 游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。 4、 亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。 5、 用数码管显示获胜者的盘数。教学提示: 1、 按钮信号即输入的脉冲信号，每按一次按钮都应能进行有效的计数。 2、 用可逆计数器的加、减计数输入端分别接受两路脉冲信号，可逆计数器原始输出状态为0000，经译码器输出，使中间一只二极管发亮。 3、 当计数器进行加法计数时，亮点向右移；进行减法计数时，亮点向左移。 4、 由一个控制电路指示谁胜谁负，当亮点移到任一方终端时，由控制电路产生一个信号，使计数器停止计数。 5、 将双方终端二极管“点亮”信号分别接两个计数器的“使能”端，当一方取胜时，相应的计数器进行一次计数，这样得到双方取胜次数的显示。 6、 设置一个“复位”按钮，使亮点回到中心，取胜计数器也要设置一个“复位”按钮，使之能清零。
1, design a circuit can be a tug of war game. 2, the circuit using the 15 (or 9) light-emitting diodes, only after the middle of a bright start, namely the center of a tug of war. 3, games, and each side holding a button, rapidly and constantly pressed to produce pulses, who according to fast, to whom the direction of bright spots on the move, every time, bright spots move once. 4, highlights the terminal diode when the move to either party, the party would win, this time the two sides had no role in the button, the output to maintain, and only reset after so bright to restore to the center. 5, digital tube display the number of the winner of the plate. Teaching tips: 1, buttons, signals that the input pulse signal, every time I press the button should be able to effectively count. 2, with reversible counter to add, subtract count input pulse signal, respectively to accept two-way, reversible, the original output of the counter state 0000, via decoder output, so that the middle of an L (2009-12-15, VHDL, 6KB, 下载22次)