单轮三级流水结构SM4算法，该结构电路比传统流水线具有明显的资源消耗优势，而且比单轮迭代SM4算法具有更快加解密运算速度，实现更大的吞吐率。
Single round three pipeline structure SM4 algorithms, the circuit structure than conventional lines, with obvious advantages of resource consumption, and more than a single iteration SM4 faster encryption and decryption algorithm computing speed, greater throughput. (2016-06-01, VHDL, 6KB, 下载7次)
自己写的rc4加解密算法部分的verilog代码，可综合，供大家参考
Write your own encryption algorithm verilog codes rc4 section can be integrated, for your reference (2016-02-16, VHDL, 2KB, 下载19次)
实现des加密芯片的设计与实现，包括了源代码，加解密设计。
DES encryption chip design and implementation, including source code, encryption and decryption design. (2013-05-18, VHDL, 20KB, 下载1次)
改进的基2 Montgomery算法，解决了大素数的加解密运算问题
Improved base 2 Montgomery algorithm to solve the encryption and decryption of large prime numbers computing problems
(2011-10-19, VHDL, 3KB, 下载44次)
基于FPGA的DES加解密系统的实现，希望对大家有帮助
FPGA-based implementation of DES encryption and decryption system (2011-05-30, VHDL, 907KB, 下载6次)
基于FPGA的3-des加解密系统的实现
FPGA-based 3-des encryption system implementation (2011-05-30, VHDL, 260KB, 下载9次)
DES的加解密算法的实现，无错，非常适合毕业设计运用
DES encryption and decryption algorithm, error-free (2010-05-14, VHDL, 13KB, 下载38次)
将猫映射(cat map ) 与Logist ic 映射相结合, 构造了一种语音加密算法. 该算法首先将语音数据堆叠成二维,
然后利用二维猫映射将数据的位置置乱, 最后利用一维Logist ic 映射构造替换表, 对数据进行扩散.
The cat map (cat map) and Logist ic mapping the combination of a voice encryption algorithm is constructed. The algorithm first voice data stacked into two-dimensional, and then use two-dimensional cat map the location of the data scrambling and finally the use of one-dimensional Logist ic mapping structure to replace the table, the data spread. (2010-03-16, VHDL, 379KB, 下载75次)
AES 加解密 代码, 有文档说明，testbench
AES encoding decoding source code in HDL (2009-06-23, VHDL, 228KB, 下载100次)
3des10m性能优化设计代码，供加脱密适应，规模9000门
Performance Optimization 3des10m design code for the increase from Micronesia to adapt, scale 9000 (2008-12-12, VHDL, 9KB, 下载1次)
这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.
This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz. (2008-11-11, VHDL, 290KB, 下载104次)