[Windows编程] 4
-数字前面加0x表示该数是十六进制的数，0x00就是十六进制的00--//
//--P0口一共有8个IO口，即从P0.0到P0.7，而0x00二进制就是0000 0000
Before the number, add 0 to indicate that the number is hexadecimal, and 0x00 is hexadecimal (2020-01-05, VHDL, 298KB, 下载0次)
[Windows编程] yi-wei-er-jin-zhi-quan-jia-qi
一位二进制全加器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3
A binary full source code and detailed documentation WORD, maxplus software running, pin has been configured, EP1K30TC144-3 (2014-01-13, VHDL, 130KB, 下载2次)
[Windows编程] counter_5_reversible
带置位的同步可逆（加1或减1）5进制计数器。
Reversible synchronous with the set (plus one or minus 1) 5 binary counter. (2009-08-31, VHDL, 321KB, 下载6次)
[Windows编程] example3
Example3 加/减法计数器
本例程实现的是一个加/减8 进制计数器。其中包括时钟输入、使能信号、加减控制信
号、复位信号、三位输入和一位进位位。
Example3 add/subtract counter implementation of this routine is a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit. (2009-08-26, VHDL, 25KB, 下载27次)
[Windows编程] readdata_new11
用计数器产生8421码，并将所产生的8421码转化为余三码并加实验报告，波形图
Generated by counter 8421 yards, and generated more than 8421 yards 3 yards into and report on additional experiments, wave (2009-06-29, VHDL, 16KB, 下载8次)
[Windows编程] FAdder
全加器的设计，实现二进制的加法，一个输出为进位，一个输出为计算值。
全加器的设计，实现二进制的加法，一个输出为进位，一个输出为计算值。 (2009-06-29, VHDL, 3KB, 下载2次)
[Windows编程] FixToFloat
将16位二进制有符号纯小数转换为32位单精度浮点数。实际应用时，最好加tsu、tco约束条件，速度会快些。
There will be 16-bit binary decimal symbol is converted to pure 32-bit single precision floating point. Practical applications, it is best to increase tsu, tco constraints, the speed will be faster. (2008-11-09, VHDL, 1KB, 下载34次)
[Windows编程] MyClock
可调时钟
实验要求：1.能正常显示一天24小时时间
2.具有清零、各位均可调功能
3.按钮设置防抖
4.可调不能通过将该位置零，然后用计数器连续加1的方法实现，并且实现每一位都单独可调
Adjustable clock Experimental requirements: 1. To show the normal 24 hours a day 2. Has cleared, you can transfer function 3. Button to set up Anti-Shake 4. Adjustable position can not be zero, and then use the counter of one continuous method, and realize every single adjustable (2008-08-27, VHDL, 477KB, 下载3次)
[Windows编程] anEncryptesystem
加解密的一个方案了,关于"椭圆"的理论和算法
Encryption and decryption of a program, and on the (2008-08-09, VHDL, 399KB, 下载3次)
[Windows编程] yibuqinglin
含异步清0和同步时钟使能的4位加法计数器
含计数使能,异步复位和计数值并行预置功能4位加法计数器,由实验图1所示,图中间是4位锁存器 rst是异步清信号,高电平有效 clk是锁存信号 D[3..0]是4位数据输入端.当ENA为 1 时,多路选择器将加1器的输出值加载于锁存器的数据端 当ENA为 0 时将"0000"加载于锁存器.
With asynchronous and synchronous clock clearance 0 enabled four adder counter with count enable, asynchronous reset and preset functions of numerical parallel adder four counters, by the experiment shown in Figure 1, Figure 4 middle latch rst is asynchronous clearance signal, high effective signal clk is Latched D [3 .. 0] is 4-bit data input. When ENA for 1:00, MUX will increase the output value of 1 load in latch data terminal when the ENA for the 0:00 to 0000 add-in latch. (2008-06-28, VHDL, 62KB, 下载7次)
[Windows编程] bank
基于模型机的设计，进行简单的CPU设计并实现基本的指令，如加、减、转移等。
Model-based design, a simple CPU design and realization of the basic commands, such as add, subtract, transfer. (2008-06-27, VHDL, 1501KB, 下载15次)
[Windows编程] 1002016p_Sa
设计一个两位全加器，并用发光二极管显示结果。全加器的三个输入（二个数字输入，一个进位输入）用实验箱中W1,SW2,SW3控制，二个输出用发光管LED1,LED2显示。整个设计采用层次设计方法，顶层文件采用原理图输入法。整个电路设计思路分三部分：
1半加器电路设计；
2.全加器电路设计，是在半加器的基础上设计的；
3.数据输入，输出电路设计。
The design of a two full-adder, and the result will be displayed using light-emitting diodes. Full adder of the three inputs (two digital input, a binary input) with the experimental box W1, SW2, SW3 control, two output with LED LED1, LED2 display. Used throughout the design-level design methodology, the top-level schematic document using the input method. The whole circuit design divided into three parts: one half adder circuit design 2. Full adder circuit design, in the half adder based on the design 3. Data input and output circuit design. (2008-04-20, VHDL, 34KB, 下载4次)