[其他] experiment
用quartus，，VHDL语言实现半加器，全加器
Realize half adder and full adder (2020-07-08, VHDL, 2948KB, 下载0次)
[其他] 实验2全加器的设计
eda实验报告包含8位全加器和16位全加器
EDA experiment report includes 8-bit full adder and 16 bit full adder (2020-07-03, VHDL, 58KB, 下载1次)
[其他] jiafa
半加器的代码，以及ucf文件，仿真已过，可在basys2上运行
The code of the semi adder, as well as the UCF file, has passed the simulation and can be run on basys2 (2020-05-03, VHDL, 933KB, 下载0次)
[其他] h_adder
这是一个半加器的编码，功能简单，编程简单
This is a half adder code, simple in function and programming (2020-03-19, VHDL, 1483KB, 下载0次)
[其他] 俄罗斯方块
俄罗斯方块verilog程序代码，实现经典游戏俄罗斯方块的程序
有参考意义
可以运行
Russian Tetris Verilog Program Code to Realize the Program of the Classic Game Russian Tetris
It has reference significance.
Can run (2019-04-18, VHDL, 7KB, 下载1次)
[其他] adder
应用半加器实现一位全加器再实现 八位全加器
Implementation of a full adder by half adder and eight bit full adder (2018-09-05, VHDL, 5678KB, 下载0次)
[其他] adder8
基于vhdl的八位全加器设计及仿真 包含半加器，一位全加器等基本单元
The design and Simulation of the eight bit full adder based on VHDL include half adder, full adder and other basic units (2018-09-05, VHDL, 3025KB, 下载0次)
[其他] hadder
采用Quartus软件综合半加器结构，包含代码和综合RTL电路图
Quartus software is used to integrate half adder structure, including code and integrated RTL circuit diagram. (2018-08-27, VHDL, 2767KB, 下载0次)
[其他] fourhand
用vhdl语言实现全加法器功能，。。。。。。。
Implement full adder function in VHDL language (2018-06-11, VHDL, 2906KB, 下载0次)
[其他] 实验二
里面是全加器的代码，共五种，分别用不同语句写的
There are five kinds of code in it, which are written in different sentences. (2017-12-31, VHDL, 1KB, 下载1次)
[其他] xor8b
实现8位全加器，为初学者提供参考，对VHDL语言有一定了解
It's a addler of 8 bits,which is designed for new learners (2017-07-11, VHDL, 93KB, 下载1次)
[其他] xor4b
实现四位全加器，为初学者提供参考说明，对VHDL语言有一定了解
it's a addler of four bits,which is designed for the new learner of VHDL language (2017-07-11, VHDL, 89KB, 下载1次)
[其他] Desktop
通过调用一位全加器模块,实现四位全加器功能
By calling a full adder module, four full adder function (2012-12-29, VHDL, 1KB, 下载2次)
[其他] VHDL
加法器、寄存器、半加器、译码器的硬件描述语言的描述
describe summator ，register，half adder,decoder with VHDL (2012-05-16, VHDL, 2KB, 下载3次)
[其他] full_aller
这是基于VHDL的一位全加器设计的程序，分析过程全面
This is based on a full adder VHDL design process, a comprehensive analysis process (2010-04-07, VHDL, 4347KB, 下载10次)
[其他] f_adder
一位加法全加器，可以实现低位进位输入和高位进位输出。
full adder (2009-12-24, VHDL, 77KB, 下载6次)
[其他] AD9851_VERILOG
一个DDS芯片AD9851的VERILOG程序，加74HC574锁存器！
A DDS chip AD9851' s VERILOG program, plus 74HC574 latch! (2009-08-25, VHDL, 1KB, 下载19次)
[其他] add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过
A full adder and the VHDL source code through TEST BENCH.XILINX (2009-07-20, VHDL, 794KB, 下载49次)
[其他] hierarch_unit.tar
该代码是布斯乘法器代码，用于了解布斯算法，本人也是初学者。
err (2008-12-14, VHDL, 91KB, 下载20次)
[其他] ADDER4B
此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能
This procedure is used VHDL hardware description languages, the realization of the four full-adder function (2008-12-11, VHDL, 52KB, 下载9次)