VERILOG RTL（维罗格RTL）
VERILOG RTL (2024-01-05, Verilog, 0KB, 下载0次)
牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)
VERILOG 语言实现 AES128算法
Implementation of aes128 algorithm with Verilog language (2021-03-02, Verilog, 4KB, 下载3次)
米联客2020版FPGA课程(MIG DDR篇)-K7
FPGA course 2020 (MIG DDR) - KINTEX 7 (2020-11-09, Verilog, 3180KB, 下载30次)
数电实验FPGA verilog代码，包括秒表、全加器、半加器等。
FPGA Verilog code for digital experiment (2020-04-29, Verilog, 8KB, 下载1次)
俄罗斯方块游戏，采用Verilog编写，整个工程文件，TFT/VGA显示
Tetris game, written by Verilog, the whole project file, TFT / VGA display (2019-12-15, Verilog, 4502KB, 下载2次)
verilog语言半加器全加器好好看看吧希望对大家有用
Verilog language, half adder, full adder. Have a look. I hope it will be useful to you. (2019-10-28, Verilog, 24KB, 下载0次)
半加器实现，简单的半加器，作为新手实验用
Semi-adder implementation, simple semi-adder, as a novice experiment (2019-06-12, Verilog, 2960KB, 下载6次)
实现了4位半加器的verilog HDL代码
Implementation of Verilog code for 4-bit semi-adde (2019-06-10, Verilog, 252KB, 下载0次)
1. 利用一位半加器设计八位全加器
2. 进行功能仿真
1. Design of an eight-bit full adder by using a one-and-a-half adder
2. Functional simulation (2019-03-22, Verilog, 678KB, 下载0次)
就是用FPGA写的音频加嵌模块。代码很多慢慢看
it is Using FPGA to write audio module. (2018-10-12, Verilog, 63KB, 下载3次)
利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench
Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language (2018-08-06, Verilog, 258KB, 下载3次)
vhdl 加法器和减法器 希望对VHDL的同学有参考作用
VHDL adder and function as relative reference (2018-08-03, Verilog, 654KB, 下载12次)
俄罗斯方块用vga实现 用Verilog代码实现
Tetris is implemented by VGA and implemented by Verilog code. (2018-06-21, Verilog, 18581KB, 下载8次)
aes加解密算法源代码及testbench平台
AES source code and testbench (2018-06-08, Verilog, 84KB, 下载2次)
通过连续调用半加器组成一位全加器，再次调用一位全加器组成4位全加器。对初学者有一定的指导作用。
Through the continuous call half adder of a full adder, called again of a full adder four full adder. For beginners have a certain guiding role. (2018-05-28, Verilog, 1975KB, 下载0次)
verilog HDL实现一位半加器功能
Verilog HDL implements a half adder function (2018-05-05, Verilog, 2932KB, 下载0次)
全加器，可以实现数据的加法运算，有来自低位的进位和向高位的进位。
Full adder, data can be added to the operation, there are low from the carry and to the high carry. (2017-10-11, Verilog, 158KB, 下载3次)
一个用quartus原理图输入的全加器，
A full adder with quartus schematic input, (2017-10-03, Verilog, 1KB, 下载2次)
用半加器搭建全加器 使用Verilog语言
Using a half adder to build a full adder, using the Verilog language (2017-09-18, Verilog, 274KB, 下载1次)