转帖:AES的简单加解密模块。。。。。。。。。。。。
A Simple Encryption and Decryption Module of AES (2019-04-10, Verilog, 11KB, 下载3次)
fpga,塞林斯IP核应用。介绍波形发生器的应用。编辑方法,功能,参数。
The Xilinx LogiCORE IP Direct Digital Synthesizer (DDS) Compiler core implements high performance, optimized Phase Generation and Phase to Sinusoid circuits with AXI4-Stream compliant interfaces. (2018-06-21, Verilog, 895KB, 下载14次)