在基于MicroBlaze AXI软核的FreeRTOS上运行的闭环PID控制器与MPU-6050加速度计陀螺仪模块接口。
A closed loop PID controller running on FreeRTOS on MicroBlaze AXI based soft core interfaced with a MPU-6050 Accelerometer Gyroscope module. (2024-03-04, Verilog, 0KB, 下载0次)
米普斯卡拉，，
MIPSCALAB,, (2019-06-19, Verilog, 0KB, 下载0次)
奈维MIPS，，
NaiveMIPS,, (2015-12-22, Verilog, 0KB, 下载0次)
32位流水线MIPS CPU，使用Verilog和booth乘法算法（硬件中更快的乘法）。锡林克斯Sesign套房，
32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite, (2022-07-16, Verilog, 0KB, 下载0次)
AES加解密算法的Verilog代码，亲测有用
Verilog Code of AES Encryption and Decryption Algorithms (2019-06-24, Verilog, 417KB, 下载12次)
基于verilog hdl编写的vga接口驱动电路，加测试的功能，已测试。
The VGA interface driver circuit based on Verilog HDL, plus test function, has been tested. (2018-10-07, Verilog, 512KB, 下载2次)
使用verilog语言编写的PmodACL：三轴加速度计的驱动程序
Driver of PmodACL: three axis accelerometer written in Verilog language (2018-09-07, Verilog, 292KB, 下载0次)
曼彻斯特码的编码和解码程序，在ISE软件上可以成功实现
Manchester code encoding program can be successfully implemented on ISE software (2018-04-10, Verilog, 3KB, 下载8次)
通过4位加法器实现32位加法器，使用串行进位的方式首先设计一个8位全加器，然后在8位全加器的基础上设计实现32位全加器
A 32 bit adder is implemented through a 4 bit adder. First, a 8 bit full adder is designed using serial carry. Then, a 32 bit full adder is designed on the basis of 8 bit full adder. (2018-03-18, Verilog, 530KB, 下载3次)
自己编写的1553b总线的曼切斯特编码和解码电路
1553b encoder and decoder (2017-08-23, Verilog, 99KB, 下载13次)