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按平台查找： All Quartus II(7)

[VHDL/FPGA/Verilog] full adder

vhdl实现全加器，vhdl入门学习，vhdl简单程序
Implementation of full adder with VHDL (2021-04-08, Quartus II, 2740KB, 下载0次)

http://www.pudn.com/Download/item/id/1617863946927858.html

[VHDL/FPGA/Verilog] 加法器

半加器和全加器的Quartus II文本输入设计及其仿真波形
Text input design and simulation waveform of Quartus II for half adder and full adder (2020-05-22, Quartus II, 5KB, 下载0次)

http://www.pudn.com/Download/item/id/1590124940773796.html

[VHDL/FPGA/Verilog] liyuanlnx_IP_PLL

FPGA锁相环实验：顶层文件加底层IP文件构成 top中例化ip核pll
Experiment of Phase-Locked Loop Based on FPGA (2019-07-24, Quartus II, 390KB, 下载2次)

http://www.pudn.com/Download/item/id/1563950505741028.html

[VHDL/FPGA/Verilog] liyuanlnx_key_beep

FPGA按键加蜂鸣器实验：加延时防抖+蜂鸣器
Experiments of keys and buzzers in FPGA (2019-07-24, Quartus II, 379KB, 下载2次)

http://www.pudn.com/Download/item/id/1563950404999685.html

[VHDL/FPGA/Verilog] 12进制可逆计数器

12进制的加减计数器，X=1时为加，X=0时为减。
The addition and subtraction counter in the 12-digit system. Adds when X = 1 and subtracts when X = 0. (2019-06-08, Quartus II, 1556KB, 下载1次)

http://www.pudn.com/Download/item/id/1560008379687847.html

[VHDL/FPGA/Verilog] m60v20161109

实现两位数从0到100的计时，每一秒加一。
The timing of two digits from 0 to 99 (2018-07-09, Quartus II, 268KB, 下载1次)

http://www.pudn.com/Download/item/id/1531103334710256.html

[VHDL/FPGA/Verilog] EDAadd

全加器Full adder schematic waveform diagram
Full adder schematic waveform diagram (2017-10-13, Quartus II, 2902KB, 下载1次)

http://www.pudn.com/Download/item/id/1507899125521770.html

总计:7