一本关于赛灵思Zynq-7000 All Programmable（SoC）的书，是由一群来自英国格拉斯哥斯特拉斯克莱德大学（University of Strathclyde）的作者编撰，并得到了赛灵思的支持，书的作者想打造一本易懂可读的读本，让那些刚刚开始接触Zynq和已经在用Zynq的工程师从中受益，并成为工程师们手头的开发圣经。
A book on the Xilinx Zynq-7000 All Programmable (SoC) book by a group of authors the United Kingdom Glasgow Strathclyde University (University of Strathclyde) compilation, and has been supported by Xilinx, the book the authors would like to create a readable and understandable readers, let those who are just getting started with Zynq and already benefit using the Zynq engineer, and an engineer who developed the Bible at hand. (2014-11-08, Unix_Linux, 23131KB, 下载93次)
用一位全加器组成四位全加器.
所用语言是Verilog HDL.
主要用在加法器的设计中。
All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design. (2006-01-14, Unix_Linux, 3KB, 下载45次)
该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。
the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder. (2005-11-15, Unix_Linux, 21KB, 下载19次)