[VHDL/FPGA/Verilog] S6_VGA_change

verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，
Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off, (2007-09-09, Others, 2512KB, 下载177次)