[VHDL/FPGA/Verilog] Verilog-HDL
王金明的verilog实例书籍，列举了很多verilog实现的例子
verilog design example (2016-06-14, Windows_Unix, 111KB, 下载1次)
[VHDL/FPGA/Verilog] US-Navy-VHDL-Modelling-Guide
该标准的硬件和可靠性项目的产品（SHARP），技术独立电子产品的代表（TIREP）工程美国海军研究实验室（NRL），海军的合作努力水面作战中心（NSWC）开发FPGA的使用标准。
A Product of the Standard Hardware And Reliability Program (SHARP),
Technology Independent Representation of Electronic Products (TIREP)
Project
A cooperative effort of the Naval Research Laboratory (NRL), the Naval
Surface Warfare Center (NSWC) (2015-08-13, Windows_Unix, 897KB, 下载4次)
[VHDL/FPGA/Verilog] motor2
Verilog编程实现步进电机的单双八拍的四路脉冲信号。采用28BYJ-48步进电机（驱动ULN2003）验证可以实现其正反转。
Single and double eight four-shot pulse signal Verilog Programming stepper motor. Using 28BYJ-48 stepper motor (driver ULN2003) verification can achieve its inversion. (2014-04-11, Windows_Unix, 331KB, 下载20次)
[VHDL/FPGA/Verilog] dual
DDR2双内存切换程序部分代码,用于VHDL的FPGA开发
DDR2 dual memory switching part of the program code for VHDL-FPGA development (2013-05-22, Windows_Unix, 5KB, 下载2次)
[VHDL/FPGA/Verilog] dp_ram
双口RAM的设计，采用Verilog HDL语言编写。
Dual-port RAM design, using Verilog HDL language. (2010-10-29, Windows_Unix, 2KB, 下载50次)
[VHDL/FPGA/Verilog] dual_RAM
actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码
actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL (2010-09-20, Windows_Unix, 594KB, 下载90次)
[VHDL/FPGA/Verilog] RAM
双口RAM Verilog描述
双口RAM Verilog描述
双口RAM Verilog描述
Dual-port RAM Verilog description of dual-port RAM Verilog description of dual-port RAM Verilog description of (2010-01-11, Windows_Unix, 15KB, 下载225次)
[VHDL/FPGA/Verilog] 一些译码器源代码
内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码
decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code (2005-10-28, Windows_Unix, 4KB, 下载259次)
[VHDL/FPGA/Verilog] 一些VHDL源代码
内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序
within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM (2005-10-28, Windows_Unix, 44KB, 下载198次)
[VHDL/FPGA/Verilog] 相位差可调的双通道信号发生器的设计
相位差可调的双通道信号发生器的设计,可以作为信号源用
phase difference adjustable dual-channel signal generator, we can use as a signal source (2005-09-07, Windows_Unix, 302KB, 下载57次)