SystemVerilog中的AES IP设计，使用双时钟并支持可重新配置的SBox和时序。
An AES IP design in SystemVerilog, ultilizing dual clocks and supporting reconfigurable SBox and timing. (2024-03-06, C, 0KB, 下载0次)
2017.9-2018.1与樊Xi和刘汉耀合作的微型项目
2017.9-2018.1 microe project with Fan Xi & Liu Hanyao (2018-01-11, C, 5KB, 下载0次)
在混合多核系统上运行机电一体化系统代码（XilinxZynq：双核ARM和FPGA）
Run mechatronic systems code on a hybrid multicore system (Xilinx Zynq: dual- core ARM and FPGA) (2014-07-14, C, 2641KB, 下载0次)
双摄像头，带USB 3.0接口，使用MAX10 FPGA和CYUSB3014同步从属模式。
Dual camera with USB 3.0 interface using MAX10 FPGA and CYUSB3014 synchronous slave mode. (2021-12-19, C, 59KB, 下载0次)
一种用于心电双功能AI分析的全映射节能FPGA加速器
A Fully-mapped and Energy-efficient FPGA Accelerator for Dual-function AI- based Analysis of ECG (2022-12-20, C, 41424KB, 下载0次)
基于AT86RF215收发器和IQ LVDS FPGA DDR（双数据速率）接口的SDR设计
SDR design based on the AT86RF215 transceiver with IQ LVDS FPGA DDR (dual- data-rate) interface (2022-07-27, C, 14137KB, 下载0次)
我和我的合作伙伴从头开始为我们的计算机操作基础创建了一个完全管道化的数字计算机数据路径...
My partner and I created from scratch a fully pipe-lined digital computer datapath for our Fundamentals of Computer Organization Class, which we programmed solely in verilog and implemented in Xlinx s Vivado Design Suite 2017.2. Our digital datapath optimally runs sets of MIPS Assembly instructions in hex for conducting a full search based (2020-01-27, C, 23882KB, 下载0次)