这是一个由BOOM（北航OO大师）团队创建和完成的项目。这是一个具有13级无序双发射架构的超标量处理器。
This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dual-emission architecture. (2024-08-24, SystemVerilog, 0KB, 下载0次)
超标量双问题RISC-V处理器
Superscalar dual-issue RISC-V processor (2024-07-31, SystemVerilog, 0KB, 下载0次)
全参数化双代理UART的验证IP
Verification IP of fully parameterized two agents UART (2024-07-24, SystemVerilog, 0KB, 下载0次)
双时钟fifo的系统verilog设计与验证
System verilog design and verification of a dual clock fifo (2024-06-22, SystemVerilog, 0KB, 下载0次)
再现Atari 2600、Atari 8位系列、Apple II、任天堂娱乐系统、Commodore 64、Atari-Lynx和BBC Micro中使用的mos 6502 cpu
Recreation of the mos 6502 cpu used in the Atari 2600, Atari 8-bit family, Apple II, Nintendo Entertainment System, Commodore 64, Atari Lynx, and BBC Micro (2024-06-03, SystemVerilog, 0KB, 下载0次)
团队合作ECE 593最终项目的回购
Repo for team to collaborate on the final project for ECE 593 (2024-05-27, SystemVerilog, 0KB, 下载0次)
数字光盘塔勒初级实验室。
Primer laboratorio del Taller de Dise o Digital. (2024-02-18, SystemVerilog, 0KB, 下载0次)
用于Tang Primer 25K FPGA的超级任天堂娱乐系统
Super Nintendo Entertainment System for Tang Primer 25K FPGA (2024-01-07, SystemVerilog, 0KB, 下载0次)
纯FPGA双三次插值四次实时视频上采样
Realtime video upsampling by four times using bicubic interpolation purely on FPGA (2023-12-16, SystemVerilog, 0KB, 下载0次)
具有统一内存和地址总线的双核处理器。，
2-core Processor with Unified Memory and Address Bus., (2023-09-27, SystemVerilog, 0KB, 下载0次)
MIPS 32位处理器-全功能共享内存双核处理器，具有用于缓存一致性的MSI，
MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency, (2017-06-01, SystemVerilog, 0KB, 下载0次)
双核处理器设计，
Dual Core Processor design, (2018-10-25, SystemVerilog, 0KB, 下载0次)
ITESO与INTEL合作的Bootcamp Pre-Silion验证类家庭作业和项目库，
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL, (2022-01-10, SystemVerilog, 0KB, 下载0次)
在SystemVerilog中实现双问题流水线多媒体处理器体系结构（SONY Cell SPU），
Implementation of a Dual Issue Pipelined Multimedia Processor Architecture (SONY Cell SPU) in SystemVerilog, (2016-09-26, SystemVerilog, 0KB, 下载0次)
GCET231和UFRB的长期合作列表。
Lista de roteiros práticos desenvolvidos ao longo do curso GCET231 na UFRB. (2022-11-29, SystemVerilog, 9753KB, 下载0次)
APV21B-实时视频16X双立方体超分辨率IP，兼容AXI4流视频接口，4K 60FPS
APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS (2023-03-09, SystemVerilog, 448KB, 下载0次)
创建一个高级GPU的合作项目，具有额外的功能来充实家庭疯狂的外围设备...
Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer. (2023-02-26, SystemVerilog, 121700KB, 下载0次)
在中设计并测试了一个FPGA芯片，用于与另一个合作伙伴控制四旋翼机。它通过无线方式接收命令...
Designed and tested an FPGA chip in to control the quadcopter with another partner. It receives commands wirelessly with a long-range Bluetooth module with a UART interface and gets the data from the inertial sensor with SPI to control the ESC motor. It was designed with the system Verilog and was also synthesized with Synopsis Design Vision. (2022-06-01, SystemVerilog, 34KB, 下载0次)
一阶德尔塔-西格玛调制器的可综合系统Verilog IP核
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator (2020-06-06, SystemVerilog, 2KB, 下载0次)
使用verilog和系统verilog的双时钟双端口ram
dual clock dual port ram using verilog and system verilog (2020-11-24, SystemVerilog, 5KB, 下载0次)