双时钟fifo的系统verilog设计与验证
System verilog design and verification of a dual clock fifo (2024-06-22, SystemVerilog, 0KB, 下载0次)
用于Tang Primer 25K FPGA的超级任天堂娱乐系统
Super Nintendo Entertainment System for Tang Primer 25K FPGA (2024-01-07, SystemVerilog, 0KB, 下载0次)
ITESO与INTEL合作的Bootcamp Pre-Silion验证类家庭作业和项目库，
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL, (2022-01-10, SystemVerilog, 0KB, 下载0次)
在SystemVerilog中实现双问题流水线多媒体处理器体系结构（SONY Cell SPU），
Implementation of a Dual Issue Pipelined Multimedia Processor Architecture (SONY Cell SPU) in SystemVerilog, (2016-09-26, SystemVerilog, 0KB, 下载0次)
GCET231和UFRB的长期合作列表。
Lista de roteiros práticos desenvolvidos ao longo do curso GCET231 na UFRB. (2022-11-29, SystemVerilog, 9753KB, 下载0次)
APV21B-实时视频16X双立方体超分辨率IP，兼容AXI4流视频接口，4K 60FPS
APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS (2023-03-09, SystemVerilog, 448KB, 下载0次)
创建一个高级GPU的合作项目，具有额外的功能来充实家庭疯狂的外围设备...
Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer. (2023-02-26, SystemVerilog, 121700KB, 下载0次)
在中设计并测试了一个FPGA芯片，用于与另一个合作伙伴控制四旋翼机。它通过无线方式接收命令...
Designed and tested an FPGA chip in to control the quadcopter with another partner. It receives commands wirelessly with a long-range Bluetooth module with a UART interface and gets the data from the inertial sensor with SPI to control the ESC motor. It was designed with the system Verilog and was also synthesized with Synopsis Design Vision. (2022-06-01, SystemVerilog, 34KB, 下载0次)
一阶德尔塔-西格玛调制器的可综合系统Verilog IP核
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator (2020-06-06, SystemVerilog, 2KB, 下载0次)
使用verilog和系统verilog的双时钟双端口ram
dual clock dual port ram using verilog and system verilog (2020-11-24, SystemVerilog, 5KB, 下载0次)
YM2149 AY-3-8910系统Verilog和Verilog中的可编程声音发生器。提供双PSG，可编程立体声m...
YM2149 / AY-3-8910 Programmable Sound Generator in SystemVerilog and Verilog. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built-in floating point system clock divider/generator. (2022-09-08, SystemVerilog, 166KB, 下载0次)
开发了一种基于SONY Cell SIMD ISA的双问题流水线多媒体处理器，具有2块直接映射缓存...
Developed a Dual-issue Pipelined Multimedia Processor based on SONY Cell SIMD ISA with 2 block direct mapped cache. ? The functional design was created in System Verilog and parser script in PERL that converts Assembly language to 32 bit of instructions. ? Successfully detected and resolved all the hazards like Data Hazards (RAW & WAW), (2017-10-29, SystemVerilog, 914KB, 下载0次)