[VHDL/FPGA/Verilog] vcpwmcpldcar
vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码
vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code (2007-09-27, MultiPlatform, 937KB, 下载72次)
[VHDL/FPGA/Verilog] my_ramlib_06
包括各种类型存储器的VHDL描述，如FIFO，双口RAM等
including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc. (2006-10-20, MultiPlatform, 601KB, 下载118次)
[VHDL/FPGA/Verilog] 双路脉冲发生器（veralog）
Verilog HDL 程序
双路脉冲发生器的代码
包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块
是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com
Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is written I hope to help you, it can be mail : shaojunwu1@163.com (2005-12-13, MultiPlatform, 4KB, 下载142次)
[VHDL/FPGA/Verilog] ddr_verilog_xilinx
DDR（双速率）SDRAM控制器参考设计，xilinx提供
DDR (double data rate) SDRAM controller reference design for Xilinx (2005-10-24, MultiPlatform, 128KB, 下载366次)