金鼎娱乐合作Ｑ2082692670双凤塔下载搜索联合开发网

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按平台查找： All Visual C++(19)

[VHDL/FPGA/Verilog] top6

fpga2分屏代码，实现dvi输入视频信号，双路dvi输出视频信号，完成1分2
fpga2 split-screen code to achieve dvi input video signal, dual dvi output video signal, completed 1 of 5 (2014-02-17, Visual C++, 12442KB, 下载5次)

http://www.pudn.com/Download/item/id/2463567.html

[VHDL/FPGA/Verilog] 2012CPLD

CPLD处理双旋变的程序，与单旋变类似，可以参考下
CPLD with a double spin transition program, similar to the single resolver, you can refer to the following (2014-02-12, Visual C++, 1KB, 下载3次)

http://www.pudn.com/Download/item/id/2461091.html

[VHDL/FPGA/Verilog] IDT7007

双口RAM，亲测试可以用。各个IO口可以自己看资料。绝对正确
DOUBLE RAM (2013-08-29, Visual C++, 262KB, 下载6次)

http://www.pudn.com/Download/item/id/2342697.html

[VHDL/FPGA/Verilog] mutil_cpu

主要设计了基于Nios_的双核处理器的设计与实现，内含QUARTUS工程文件，实现了两个CPU通过互斥核通讯的实验。EP2C5平台
Primarily designed dual-core processors based Nios_ the design and implementation of embedded QUARTUS engineering documents, to achieve a of two CPU mutex nuclear communications experimental. EP2C5 platform (2013-04-02, Visual C++, 22338KB, 下载14次)

http://www.pudn.com/Download/item/id/2182978.html

[VHDL/FPGA/Verilog] PCI_5Vjinshouzhi

PCI通用金手指的定义和说明，还有不同金手指的说明
The definition and description of the PCI Universal Goldfinger, there are different Goldfinger instructions (2013-03-27, Visual C++, 6KB, 下载7次)

http://www.pudn.com/Download/item/id/2175214.html

[VHDL/FPGA/Verilog] abc

线性反馈与对偶移位寄存器的功能实现实现n-LFSR与 n-DSR（n为正整数）进动一拍的程序（旨在能“由寄存器的一个状态算出紧接着的下一个状态”）寄存器状态的各分量自然地与相应数据存储区的各比特位一一对应，不允许仅1个状态分量就占据1个存储单元（字节、字或双字等）。
Linear feedback shift register with dual function realization The realization of n-LFSR and n-DSR ( n is a positive integer ) precession pat program ( " by the register to a state to calculate the immediate next state ." ) Register status of each component of naturally with the corresponding data storage area of the corresponding bits one one, do not allow only 1 state component will occupy the 1 storage unit ( byte, word or doubleword etc.). (2012-12-21, Visual C++, 174KB, 下载8次)

http://www.pudn.com/Download/item/id/2091677.html

[VHDL/FPGA/Verilog] 03-Pattern-Horse-Light

花样流水灯，具有单灯，双灯及多灯显示功能，具体请看图案，过多无法详细说明
Mood light water, a single lamp, dual-lamp and multi-lamp display function, see the specific pattern, too much can not be described in detail (2012-10-17, Visual C++, 12KB, 下载6次)

http://www.pudn.com/Download/item/id/2018418.html

[VHDL/FPGA/Verilog] shuangPWM

基于xs128的双路pwm波程序,可供初学者使用。
this is a (2012-08-09, Visual C++, 249KB, 下载5次)

http://www.pudn.com/Download/item/id/1961759.html

[VHDL/FPGA/Verilog] TVerrilog_Exae

王金明老师讲述的100个Verilog代码示例，并附带有相关关说明，Verilog初学入门者非常好的入门资料！已通过测试。
100 Wang Jinming teacher tells the Verilog code examples, together with an off the Verilog novice beginners to very good introductory information! Has been tested. (2012-07-26, Visual C++, 166KB, 下载3次)

http://www.pudn.com/Download/item/id/1949041.html

[VHDL/FPGA/Verilog] Acostas_PLLc

实现科斯塔斯环，pll程序，仿仿真通过，matlab程序-pll
Costas loop pll program, through imitation simulation, matlab program-pll (2012-07-18, Visual C++, 1KB, 下载11次)

http://www.pudn.com/Download/item/id/1942398.html

[VHDL/FPGA/Verilog] TLV5618

TLV5618可编程双路12位数模转换器产生三角波正弦波
The TLV5618 Programmable Dual 12-bit DAC and the triangle sine wave (2012-07-09, Visual C++, 19KB, 下载23次)

http://www.pudn.com/Download/item/id/1933573.html

[VHDL/FPGA/Verilog] SHOOK16

[功能特点] ----------------------------------------------------------------------- # 创新设计16个LED灯的摇摇棒，可显示英文、图形及汉字 # 仅需5种元器件（单片机、LED、导线、电池和塑料壳），让DIY简单、快速 # 往返双程扫描，慢速摇动也可清晰显示 # 敲击字幕切换功能，无需按键操作 # 在软件上有很大的升级空间（包括双色显示、LED测光等）
[功能特点] ----------------------------------------------------------------------- # 创新设计16个LED灯的摇摇棒，可显示英文、图形及汉字 # 仅需5种元器件（单片机、LED、导线、电池和塑料壳），让DIY简单、快速 # 往返双程扫描，慢速摇动也可清晰显示 # 敲击字幕切换功能，无需按键操作 # 在软件上有很大的升级空间（包括双色显示、LED测光等） (2012-06-09, Visual C++, 3KB, 下载5次)

http://www.pudn.com/Download/item/id/1907900.html

[VHDL/FPGA/Verilog] Double-byte-adder-BCD-code

将以片内RAM 30H 为起始地址的双字节BCD码 30H和40H为起始地址的双字节BCD码相加，结果放在50H和51H中，程序结束
Will be in RAM30H for the starting address of the double byte BCD code 30H and 40H for the starting address of the double byte BCD code phase, results in 50H and 51H, end of program. (2012-05-04, Visual C++, 41KB, 下载2次)

http://www.pudn.com/Download/item/id/1855352.html

[VHDL/FPGA/Verilog] 1TP8051

1T+8051单片机单串口双串口3串口测试程序.
1T+8051 chip dual-port 3 single serial port test program. (2011-08-12, Visual C++, 3KB, 下载4次)

http://www.pudn.com/Download/item/id/1620370.html

[VHDL/FPGA/Verilog] UHF-RFID-CRC

本文首先研究了IsO／IECl8000．6标准中A、B两类短程通讯的前向链路与返回链路的数据编码方式，对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码的编解码方式和技术参数进行了深入的分析，并利用FPGA实验平台对这三种编码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理进行了探讨，重点研究了ISo／IECl8000．6标准中采用的数据保护与校验技术，即循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现CRC的电路，从理论和实现两个方面对其中存在的问题提出了解决办法，设计了一种改进型线性反馈移位寄存器电路来实现循环冗余校验。对于要求CRC运算速度高的系统，本文利用了递归的算法设计了一种新型的并行CRC电路。最后本文提出了一种新颖的UHF RFID系统数字基带电路，区别于一般数字基带电路的地方是：在编解码模块和CRC模块之间加入了卷积编码和维特比译码模块。利用卷积码优良的纠错能力，来解决UHF RFID系统在电磁干扰严重的环境中识别率低、通信速度慢的问题，效果良好。
The first，this paper investigates the f．0rward link and retum link data encodlng method in short range communication types A and B in ISO／IEC 1 8000-6，and deeply analyzes encoding method and technical parameters of Bi—Phase Space(FMO)coding， Pulse IntervaI Encoding(PIE)coding and Manchester coding．We also designed and simulated code circuits and decode circuits of the three encoding method by FPGA experiment platfoml． The second， We discussed the technical principle of error control of the UHF RFID system，especially for the techn0109y of data Verification 肌d calibration，namely cyclic redundancy check that used in IS0／IEC 1 8000·6·The circuits of CRC based on Linear Feedback Shin Register(LSFR)are analyzed行om theonr and realization，and some means of solVing problems are put fon)Irard，then an improved LSFR circuit to implement CRC is designed．For some require fast CRC calculation system，we designed a noVel parallel CRC circuit by using recurslVe fomlula．In the end，we put forw (2011-02-14, Visual C++, 4264KB, 下载69次)

http://www.pudn.com/Download/item/id/1428206.html

[VHDL/FPGA/Verilog] 100111210253

关于ＦＰＧＡ显示的程序，很实用，希望旅游时间下载，如有合作的请加我ＱＱ
ａｂｏｕｔ　ｔｈｅ　ｃｏｄｅ　ｏｆ　ＦＰＧＡ (2010-07-06, Visual C++, 948KB, 下载3次)

http://www.pudn.com/Download/item/id/1233249.html

[VHDL/FPGA/Verilog] W629---6225

仿三星W629 MT6225 CPU双卡双待多国语言资料
W629 (2009-05-30, Visual C++, 8260KB, 下载12次)

http://www.pudn.com/Download/item/id/784359.html

[VHDL/FPGA/Verilog] i2c

双总线I2C测试程序，已经通过，希望对大家有帮助！
Dual Bus I2C test procedure has been adopted, we would like to help! (2009-04-30, Visual C++, 3KB, 下载2次)

http://www.pudn.com/Download/item/id/737913.html

[VHDL/FPGA/Verilog] cd4000x

CD4000 双3输入端或非门+单非门 TI 　　CD4001 四2输入端或非门 HIT/NSC/TI/GOL 　　双4输入端或非门 NSC 　　CD4006 18位串入/串出移位寄存器 NSC 　　CD4007 双互补对加反相器 NSC 　　CD4008 4位超前进位全加器 NSC 　　CD4009 六反相缓冲/变换器 NSC 　　CD4010 六同相缓冲/变换器 NSC 　　CD4011 四2输入端与非门 HIT/TI 　　CD4012 双4输入端与非门 NSC 　　CD4013 双主-从D型触发器 FSC/NSC/TOS 　　CD4014 8位串入/并入-串出移位寄存器 NSC 　　CD4015 双4位串入/并出移位寄存器 TI 　　CD4016 四传输门 FSC/TI 　　CD4017 十进制计数/分配器 FSC/TI/MOT 　　CD4018 可预制1/N计数器 NSC/MOT
CD4000-cd4066 (2009-04-29, Visual C++, 2366KB, 下载20次)

http://www.pudn.com/Download/item/id/736503.html

总计:19