[嵌入式/单片机/硬件编程] fpu_double
F双精度，，
fpudouble,, (2021-01-28, VHDL, 0KB, 下载0次)
[嵌入式/单片机/硬件编程] OS2018spring-projects-g05
双核MIPS CPU SoC，
Dual-core MIPS CPU SoC, (2018-09-26, VHDL, 0KB, 下载0次)
[嵌入式/单片机/硬件编程] 单片机实验报告2
1.学习单片机简单扩展输出I/O接口的方法。
2.学习控制模拟交通灯的方法。
3.学习双色灯的使用。
1. Learn the method of simple extension output I/O interface for single chip microcomputer.
2. Learn to control the simulation of traffic lights.
Learn the use of a two-tone lamp. (2018-04-28, VHDL, 11KB, 下载1次)
[嵌入式/单片机/硬件编程] key_detect
按键检测去抖源代码，默认输入时钟为100Mhz，有上升沿、下降沿双沿检测机制。
key detect soure code,you can detect rising or falling . (2015-12-31, VHDL, 1KB, 下载2次)
[嵌入式/单片机/硬件编程] baluqiangdaqi
八路智能抢答器，适用于娱乐休闲节目中，方便快捷有效的进行各种活动
8 the intelligent vies to answer first, suitable for leisure, entertainment programs, convenient and quick effective for all kinds of activities (2011-12-21, VHDL, 125KB, 下载4次)
[嵌入式/单片机/硬件编程] lcd
组合逻辑电路设计：实现9种逻辑运算、6种移位运算以及高低双字节内容互换。
Combinational logic circuit design: Implementation of 9 logical operations, six kinds of double-byte shift operation, as well as the level of content exchange. (2010-06-05, VHDL, 3KB, 下载5次)
[嵌入式/单片机/硬件编程] TESTRAM
FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！
FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much about the use of! Simulation software platform QUARTUSII8.0 through! (2009-08-13, VHDL, 437KB, 下载270次)
[嵌入式/单片机/硬件编程] 020.pdf2
C8051F020/1/2/3
混合信号ISP FLASH 微控制器
数 据 手 册
潘 琢 金 译
C8051F020/1/2/3 Mixed-Signal ISP FLASH MCU Data Sheet Pan Jin Zhuo translation (2009-05-04, VHDL, 2372KB, 下载6次)
[嵌入式/单片机/硬件编程] dual_disp_pci
双显示的PCI卡的原理SCH 和相关PCB文件
develop dual display pci boad card sch and pcb (2009-03-25, VHDL, 772KB, 下载4次)
[嵌入式/单片机/硬件编程] fifov1
FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用
双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、
与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data）
为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和
满标志（full）以禁止读写操作。
FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations. (2008-03-31, VHDL, 370KB, 下载280次)