双核微控制器1.0版，
Dual-core Microcontroller ver1.0, (2023-09-20, Verilog, 0KB, 下载0次)
在一个3人的团队中工作，在System Verilog中从头开始完成流水线RISC-V处理器，包括双L1...
Worked on a team of 3 to complete a pipelined RISC-V processor from scratch in System Verilog, complete with dual L1 Caches, a L2 cache, prefetching, and a branch predictor. (2020-11-11, Verilog, 1182KB, 下载0次)
一个无序、双发行的RISC-V内核和SOC，一个工作项目。
An out-of-order, dual issueed RISC-V core and SOC, a working project. (2023-04-24, Verilog, 1137KB, 下载0次)
biRISC-V-32位双问题RISC-V CPU软件环境
biRISC-V - 32-bit dual issue RISC-V CPU Software Environment (2021-06-24, Verilog, 2369KB, 下载0次)
在Digilent Arty S7-50 FPGA板上实现的双核RISC-V处理器（使用PULP平台SoC）。
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. (2022-08-07, Verilog, 24792KB, 下载0次)
具有集成eFPGA的双RISC-V DISC
Dual RISC-V DISC with integrated eFPGA (2021-10-09, Verilog, 119155KB, 下载0次)
双核RISC-V SoC，带JTAG、原子、SDRAM
Dual-core RISC-V SoC with JTAG, atomics, SDRAM (2022-01-01, Verilog, 122KB, 下载0次)
双发RV64IM处理器，娱乐和学习
Dual-issue RV64IM processor for fun & learning (2023-01-18, Verilog, 6360KB, 下载0次)