本项目属于超大规模集成电路领域，主要致力于基础存储器芯片的设计。我们设计了SRAM阵列和双核ROM阵列。
This Project is of VLSI domain, mainly focuses on designing of fundamental Memory chips. We have designed SRAM Array and Dual Core ROM Array. (2024-06-05, Verilog, 0KB, 下载0次)
使用OpenLANE Sky130研讨会进行为期2周的高级物理设计，具有完整的RTL2GDSII流程，由VSD组织，作为高中芯片设计三级计划的一部分，与英特尔印度公司合作
2 Week Advanced Physical Design using OpenLANE Sky130 workshop with complete RTL2GDSII flow organised by VSD as part of Level-3 of Chip Design for High School Program in collaboration with Intel India (2024-03-28, Verilog, 0KB, 下载0次)
尤瑟斯斯塔
yosys sta (2024-03-19, Verilog, 0KB, 下载0次)
为期2周的数字VLSI SoC设计和规划研讨会，由VSD与NASSCOM合作组织完整的RTL2GDSII流程
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (2024-03-15, Verilog, 0KB, 下载0次)
该研讨会由印度工业技术研究院Guwahati与印度电子九实验室MeitY合作举办。
This workshop was organised by IIT Guwahati collabarted with MeitY, NINE Labs, Electronics India. (2024-02-06, Verilog, 0KB, 下载0次)
该存储库包含SPI_master verilog代码及其测试台。具有单总线、双总线和四总线模式的spi_master。，
This repository contains SPI_master verilog code along with its testbench. The spi_master with single, dual and quad bus modes., (2020-08-11, Verilog, 0KB, 下载0次)
点击悲伤的脸让它们消失，不要伤害快乐的脸！与合作伙伴一起创建计算机组织和逻辑课程。，
Click on the sad faces to make them disappear, don t hurt the happy faces! Created with partner for Computer Organization and Logic course., (2021-03-21, Verilog, 0KB, 下载0次)
yosys斯塔，，
yosys-sta,, (2023-08-20, Verilog, 0KB, 下载0次)
通过双Vth单元分配和栅极重新调整的后综合功率优化。使用为Sync编写的自定义命令在TCL中编写脚本...，
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys? PrimeTime? and DC Ultra?. (2021-06-09, Verilog, 0KB, 下载0次)