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[VHDL/FPGA/Verilog] 10gb_ethernet

基于A.Forencich verilog以太网的10Gb以太网解决方案外壳兼容
10Gb Ethernet solution shell compatible based on A.Forencich verilog-ethernet (2024-02-29, Python, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1709470372539480.html

[VHDL/FPGA/Verilog] fpga-netlist

fpga网表，，
fpga-netlist,, (2015-04-07, Python, 8KB, 下载0次)

http://www.pudn.com/Download/item/id/1428344576385809.html

[VHDL/FPGA/Verilog] thrust-timing

FPGA网表时序延迟计算使用NVIDIA推力库中的并行模式。
FPGA netlist timing delay calculations using parallel patterns in the NVIDIA Thrust library. (2015-03-09, Python, 1157KB, 下载0次)

http://www.pudn.com/Download/item/id/1425885094702407.html

[VHDL/FPGA/Verilog] cyborg

天网数据采集FPGA代码及接口
Skynet Data acquisition FPGA code and interfaces (2012-02-23, Python, 375KB, 下载0次)

http://www.pudn.com/Download/item/id/1329993987460721.html

[VHDL/FPGA/Verilog] netlistx

用于学术用途的FPGA网表解析器和编辑器。
A FPGA netlist parser and editor for academic use. (2017-08-24, Python, 2664KB, 下载0次)

http://www.pudn.com/Download/item/id/1503567626231062.html

[VHDL/FPGA/Verilog] netlister

类似Verilog的网表到Eagle PCB生成脚本实用程序和库
Verilog-like netlist to Eagle PCB generating script utility and libraries (2022-12-01, Python, 55KB, 下载0次)

http://www.pudn.com/Download/item/id/1669900151323645.html

[VHDL/FPGA/Verilog] netlist-paths-tests

使用第三方Verilog设计的网表路径测试套件
A suite of tests for netlist-paths, using third-party Verilog designs (2021-08-24, Python, 6KB, 下载0次)

http://www.pudn.com/Download/item/id/1629764797987883.html

[VHDL/FPGA/Verilog] birdie

促进Verilog网表跟踪的Vim插件
A Vim plugin that facilitates Verilog netlist tracing (2022-05-12, Python, 1366KB, 下载0次)

http://www.pudn.com/Download/item/id/1652337992463325.html

[VHDL/FPGA/Verilog] iverilog-netlist-processing

将Icarus Verilog网表解析为Python结构。
Parse Icarus Verilog netlists into Python structures. (2014-09-30, Python, 11KB, 下载0次)

http://www.pudn.com/Download/item/id/1412079264909530.html

[VHDL/FPGA/Verilog] Verilog-netlist-viewer

将Verilog网表显示为图形表示
Display Verilog netlist as graphical representation (2017-09-14, Python, 18KB, 下载0次)

http://www.pudn.com/Download/item/id/1505375887169578.html

[VHDL/FPGA/Verilog] VerilogParsePy

该项目的目的是从verilog文件中解析网表。这是在前阿尔法阶段，我还没有测试它...
The object of this project is to parse netlist from verilog file. This is in prealpha stage I have yet to test it on other files but the one included in project. (2019-10-13, Python, 6KB, 下载0次)

http://www.pudn.com/Download/item/id/1570937895552304.html

[VHDL/FPGA/Verilog] verilog2dimacs

将通用Verilog网表转换为与许多SAT解算器兼容的DIMACS格式
Coverts a generic Verilog netlist into the DIMACS format compatible with many SAT solvers (2020-02-25, Python, 3KB, 下载0次)

http://www.pudn.com/Download/item/id/1582637340444221.html

[VHDL/FPGA/Verilog] NetList-Viewer-and-Simulator

一个python程序，它解析verilog网表（.vm）文件并生成一个图，并与用户输入模拟该文件...
A python program that parses a verilog netlist (.vm) files and generates a graph and simulates the file with user inputs. (2021-03-31, Python, 160703KB, 下载0次)

http://www.pudn.com/Download/item/id/1617184433560060.html

[VHDL/FPGA/Verilog] py-verilog-toolkit

读取电源和地面verilog网表并生成UPF
Read power&ground verilog netlist and generate UPF (2020-03-03, Python, 154KB, 下载0次)

http://www.pudn.com/Download/item/id/1583242695658892.html

[VHDL/FPGA/Verilog] verilog2hgr

用于解析合成门级网表并输出超图文件以进行分区的脚本
Script to parse synthesized gate-level netlists and output hypergraph files for partitioning (2015-12-14, Python, 4KB, 下载0次)

http://www.pudn.com/Download/item/id/1450081623830087.html

[VHDL/FPGA/Verilog] verilog-flowgen

以太网流量生成器框架
Ethernet flow generator framework (2015-02-25, Python, 42KB, 下载0次)

http://www.pudn.com/Download/item/id/1424793843728756.html

[VHDL/FPGA/Verilog] netlist_parser

一个基于Python的网表解析器，包括Verilog和SPICE
A Python based netlist parser, including Verilog and SPICE (2015-07-24, Python, 52KB, 下载0次)

http://www.pudn.com/Download/item/id/1437691086836288.html

[VHDL/FPGA/Verilog] Verilog2Spice

结构简单的VERILOG网表到SPICE网表转换器
Simple strutured VERILOG netlist to SPICE netlist translator (2022-05-22, Python, 4KB, 下载0次)

http://www.pudn.com/Download/item/id/1653204931883146.html

[VHDL/FPGA/Verilog] nlviewer

verilog网表查看器和分析器
verilog netlist viewer and analyzer (2019-08-21, Python, 5KB, 下载0次)

http://www.pudn.com/Download/item/id/1566351536389486.html

[VHDL/FPGA/Verilog] KiCadVerilog

从KiCad网表生成Verilog代码
Generate Verilog code from a KiCad netlist (2023-05-01, Python, 74KB, 下载0次)

http://www.pudn.com/Download/item/id/1682940162831863.html