[VHDL/FPGA/Verilog] pn2vhdl
从Petri网到Vhdl
From Petri Nets to Vhdl (2024-03-15, Others, 0KB, 下载0次)
[VHDL/FPGA/Verilog] transparent_ethernet_ipv4_loadbalancer
FPGA以太网ARP IP负载平衡器。2001年的老学生项目不再在互联网上，将剩下的内容复制到github进行保存...，
FPGA Ethernet/ARP/IP load balancer. Old student project from 2001 not on the internet anymore, copied what remains to github for preservation purposes. (2018-01-30, Others, 0KB, 下载0次)
[VHDL/FPGA/Verilog] _FPGA与PC间基于PCIe和千兆以太网的通信设计
FPGA与PC间基于PCIe和千兆以太网的通信设计
Design of communication between FPGA and PC based on PCIe and Gigabit Ethernet (2020-05-13, Others, 4303KB, 下载4次)
[VHDL/FPGA/Verilog] 以太网PHY寄存器分析_
以太网寄存器分析PHY是IEEE802.3中定义的一个标准模块，STA（station management entity，管理实体，一般为MAC或CPU）通过SMI（Serial Manage Interface）对PHY的行为、状态进行管理和控制，而具体管理和控制动作是通过读写PHY内部的寄存器实现的。PHY寄存器的地址空间为5位，从0到31最多可以定义32个寄存器（随着芯片功能不断增加，很多PHY芯片采用分页技术来扩展地址空间以定义更多的寄存器，在此不作讨论），IEEE802.3定义了地址为0-15这16个寄存器的功能，地址16-31的寄存器留给芯片制造商自由定义，如表1所示。结合实际应用，对IEEE802.3定义的寄存器各项功能进行分析。
regsiter analysis for PHY. It is a standard module in IEEE802.3 (2019-12-11, Others, 266KB, 下载6次)
[VHDL/FPGA/Verilog] my_alu
一个简单的ALU程序设计，实现以下功能：
逻辑运算：与、或、非、异或、逻辑左移、逻辑右移
算术运算：加、减
A simple ALU program designed to achieve the following functions: logic operations: AND, OR, NOT, XOR logical left, logical shift right arithmetic operations: addition, subtraction (2016-05-03, Others, 580KB, 下载1次)
[VHDL/FPGA/Verilog] ethernet_test
以太网FPGA通信,verilog代码，实现双向通信
Ethernet FPGA communication (2016-01-20, Others, 2135KB, 下载36次)
[VHDL/FPGA/Verilog] ethmac10g_latest.tar
10G高速以太网mac VERILOG源码
可仿真可实现
10G high speed Ethernet MAC verilog code
can be used for synthesis or inplementation (2015-08-19, Others, 771KB, 下载40次)
[VHDL/FPGA/Verilog] fsl_net
基于FSL总线的以太网控制器,用于Microblaze系统
Ethernet controller based on FSL bus (2013-06-04, Others, 9KB, 下载5次)
[VHDL/FPGA/Verilog] fpga_UDP_NET
fpga驱动dm9000，通过网口向上位机发送数据。底层为verilog，上层Nios为c。
fpga driver dm9000, send data through the network port up crew. The underlying verilog, upper Nios c. (2013-01-05, Others, 25988KB, 下载149次)
[VHDL/FPGA/Verilog] 10_100m_ethernet-fifo
本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。
The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion. (2012-07-10, Others, 476KB, 下载8次)
[VHDL/FPGA/Verilog] DE2_115_TV
Demo program for developing a TV box using Altera DE2-115 board
Demo program for developing a TV box using Altera DE2-115 board (2011-11-23, Others, 723KB, 下载14次)
[VHDL/FPGA/Verilog] IP-UART
基于C8051F340的CP2200以太网程序
Based CP2200 Ethernet program of C8051F340 (2011-11-09, Others, 218KB, 下载19次)
[VHDL/FPGA/Verilog] NET2
FPGA中DM900A以太网控制器驱动程序开发
FPGA, DM900A Ethernet Controller Driver Development (2011-05-19, Others, 440KB, 下载20次)
[VHDL/FPGA/Verilog] FPGA
结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机
Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface (2010-05-21, Others, 379KB, 下载292次)
[VHDL/FPGA/Verilog] muxsend
调用已绑定的网口 发送vlan包。适用于再次开发中遇到网口已被底层绑定的需求。
Call the net mouth has been bound to send vlan packets. For re-development of the net mouth has been encountered in the bottom bound needs. (2010-03-19, Others, 2KB, 下载36次)
[VHDL/FPGA/Verilog] Altera_CHINESE
4篇Altera中文资料.4篇Altera中文资料
4 Altera Part .4 Chinese information Altera Chinese information (2008-01-22, Others, 442KB, 下载6次)
[VHDL/FPGA/Verilog] net_1c12_911
lan911的vhdl源代码，这是一款通用的网口芯片。
lan911 the VHDL source code, which is a common network port chip. (2008-01-21, Others, 15907KB, 下载32次)
[VHDL/FPGA/Verilog] fifowrite
ASIC 设计中 包存储功能的fifo，TCP/IP，以太网2的应用
ASIC design of storage functionality, packet fifo, TCP/IP, Ethernet 2 Application (2007-10-28, Others, 50KB, 下载67次)
[VHDL/FPGA/Verilog] ethernet__verilog
fpga模拟以太网物理层的源代码，用verilog硬件描述语言开发。
FPGA simulation of the Ethernet physical layer of the source code, using Verilog hardware description language development. (2007-09-08, Others, 323KB, 下载307次)
[VHDL/FPGA/Verilog] ethernet.tar
以太网10/100M IP核Verilog源码，可综合。
IP Ethernet 10/100 nuclear Verilog source can be integrated. (2005-11-02, Others, 913KB, 下载277次)