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[VHDL/FPGA/Verilog] fpga-stack-network

fpga中的以太网
ethernet in fpga (2019-07-26, C++, 18092KB, 下载0次)

http://www.pudn.com/Download/item/id/1564091815494552.html

[VHDL/FPGA/Verilog] Fiduccia_Matthesys-using-c-

在ISPD2016竞赛基准（FPGA合成网表）上使用C实现了网络划分的FM算法...
Implemented FM algorithm for network partitioning on ISPD 2016 contest benchmarks (FPGA Synthesized Netlists) using C++ and optimized the code for time complexity by using a linear-time heuristic presented by General Electric Research and Development Center. (2019-01-05, C++, 2940KB, 下载4次)

http://www.pudn.com/Download/item/id/1546700873548540.html

[VHDL/FPGA/Verilog] Skynet-FPGA-Acceleration

使用收缩阵列加速部分天网
Acceleration of part of Skynet using Systolic Array (2020-12-11, C++, 8919KB, 下载0次)

http://www.pudn.com/Download/item/id/1607641272763567.html

[VHDL/FPGA/Verilog] FPGAsm

一种用于FPGA的低层次网表汇编程序
A low-level hierarchical netlist assembler for FPGAs (2021-07-26, C++, 69KB, 下载0次)

http://www.pudn.com/Download/item/id/1627237225477834.html

[VHDL/FPGA/Verilog] NBGen

为verilog生成映射网表和工作台的工具
A tool to generate mapped netlist and bench for verilog (2023-04-15, C++, 54279KB, 下载0次)

http://www.pudn.com/Download/item/id/1681520145548593.html

[VHDL/FPGA/Verilog] dot2verilog

将点文件转换为Dynamatic的Verilog网表
Convert dot files to Verilog netlist for Dynamatic (2021-07-17, C++, 70KB, 下载0次)

http://www.pudn.com/Download/item/id/1626509532532127.html

[VHDL/FPGA/Verilog] NetlistParser

用于verilog网表的flex+bison解析器
flex+bison parser for verilog netlists (2016-09-28, C++, 4013KB, 下载0次)

http://www.pudn.com/Download/item/id/1475065643157594.html

[VHDL/FPGA/Verilog] verilog-nes

在Verilog中构建任天堂娱乐系统
Building a Nintendo Entertainment System in Verilog (2022-09-04, C++, 9379KB, 下载0次)

http://www.pudn.com/Download/item/id/1662279701495377.html

[VHDL/FPGA/Verilog] xge-ptpv2

用于10G以太网的PTPv2硬件引擎设计,Verilog HDL描述
Design of PTPv2 hardware engine for 10G Ethernet, described by Verilog HDL (2023-05-30, C++, 691KB, 下载0次)

http://www.pudn.com/Download/item/id/1685412532854781.html

[VHDL/FPGA/Verilog] VerilogParser

一个简单的verilog门级网表解析器
a simple parser for verilog gate level netlist (2015-11-13, C++, 11KB, 下载0次)

http://www.pudn.com/Download/item/id/1447402731464981.html

[VHDL/FPGA/Verilog] ReGDS-Logic-Gate-Extraction

一个自定义C++例程，用于识别数字电路的布局提取网表（SPICE）中的逻辑门并生成...
A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library. (2022-04-27, C++, 225KB, 下载0次)

http://www.pudn.com/Download/item/id/1651073864862894.html

[VHDL/FPGA/Verilog] netlist-paths

用于查询Verilog网表的库和命令行工具。
A library and command-line tool for querying a Verilog netlist. (2022-06-13, C++, 327KB, 下载0次)

http://www.pudn.com/Download/item/id/1655123917481123.html