银河娱乐微信16687406569官网下载搜索联合开发网

[VHDL/FPGA/Verilog] FPGalaxy

现场可编程银河-太空射击游戏
Field programmable Galaxy - space shooter game (2013-07-18, VHDL, 46KB, 下载0次)

http://www.pudn.com/Download/item/id/1374152971930992.html

[VHDL/FPGA/Verilog] digilent-xdc-master

Digilent FPGA平台，用于在vivado中便捷修改管脚xdc约束文件。也可以去digilent官网GitHub下载 digilent-xdc
Can be downloaded in Digilent GitHub. digilent-xdc (2021-04-24, VHDL, 83KB, 下载0次)

http://www.pudn.com/Download/item/id/1619234594209628.html

[VHDL/FPGA/Verilog] Xilinx_AXI

xilinx官网axi-4协议master/slave代码(verilog)
xilinx official website axi-4 protocol master/slave code (2021-04-18, VHDL, 130KB, 下载0次)

http://www.pudn.com/Download/item/id/1618741793299388.html

[VHDL/FPGA/Verilog] Altera_eth_1g10g_lineside_w_1588.tar

Altera 三速以太网 1588 官网实例
Altera trimode ethernet (2021-03-26, VHDL, 21265KB, 下载2次)

http://www.pudn.com/Download/item/id/1616729445319028.html

[VHDL/FPGA/Verilog] LEON2-master

leon2处理器的源码, 官网已经下架, 供参考
The source code of the leon2 processor, the official website has been removed, for reference (2021-01-14, VHDL, 1512KB, 下载1次)

http://www.pudn.com/Download/item/id/1610612315960854.html

[VHDL/FPGA/Verilog] xilinx_manchester_vhdl

曼彻斯特编码解码源码，基于xilinx官网介绍，内附仿真文件。
Manchester Encoder-Decoder for Xilinx CPLDs (2020-07-29, VHDL, 9KB, 下载0次)

http://www.pudn.com/Download/item/id/1595985688125906.html

[VHDL/FPGA/Verilog] xapp585

LVDS并行数据传输，来自XILINX官网
LVDS Parallel Data Transfer (2017-08-21, VHDL, 493KB, 下载25次)

http://www.pudn.com/Download/item/id/1503295461925953.html

[VHDL/FPGA/Verilog] camera

FPGA velilog hdl camera
FPGA velilog hdl camera (2015-07-30, VHDL, 60KB, 下载1次)

http://www.pudn.com/Download/item/id/1438244368871654.html

[VHDL/FPGA/Verilog] SoCKIT_Materials_14.0

SocKit FPGA with ARM core
SocKit FPGA with ARM core (2014-10-18, VHDL, 16759KB, 下载11次)

http://www.pudn.com/Download/item/id/2638016.html

[VHDL/FPGA/Verilog] fbas_encoder_latest.tar

FPGA BASELINE ENCODER (jpeg mpeg)
FPGA BASELINE ENCODER (jpeg mpeg) (2013-08-19, VHDL, 224KB, 下载14次)

http://www.pudn.com/Download/item/id/2333809.html

[VHDL/FPGA/Verilog] DE2_70

DE2-70开发板实验例程中文非官网资料
DE2-70 development board test routines Chinese non-official website information (2013-07-08, VHDL, 7025KB, 下载88次)

http://www.pudn.com/Download/item/id/2299709.html

[VHDL/FPGA/Verilog] Alrera-FPGA-SOC-Cyclone-V

Alrera FPGA SOC Cyclone V 官网开发板调试记录
Alrera FPGA SOC Cyclone V official website development board debug log (2013-06-07, VHDL, 1085KB, 下载46次)

http://www.pudn.com/Download/item/id/2272631.html

[VHDL/FPGA/Verilog] internet_test

xilinx SP605 板卡，网口设计。echo设计，实现接收单字符并返回的功能，同时从串口显示输出内容,具体流程也可以参加xilinx官网有个xapp1026的范例
Xilinx SP605 board, network port design. echo design, implementation, receiving single character and returns the output from the serial port at the same time (2013-04-18, VHDL, 12098KB, 下载27次)

http://www.pudn.com/Download/item/id/2206915.html

[VHDL/FPGA/Verilog] xapp1015

SDI接口的VHDL实现，XILINX官网的设计参考
SDI interface VHDL realize XILINX official website design reference (2013-04-16, VHDL, 596KB, 下载20次)

http://www.pudn.com/Download/item/id/2203617.html

[VHDL/FPGA/Verilog] 8259_OSED

A8259中断控制器 VHDL例程，用alteraCPLD实现，适合初学者
A8259Interrupt Controller (2012-04-08, VHDL, 112KB, 下载11次)

http://www.pudn.com/Download/item/id/1820824.html

[VHDL/FPGA/Verilog] ethmac

以太网的verilog代码，来自opencores网站。
Ethernet verilog code from opencores site. (2011-09-10, VHDL, 1763KB, 下载12次)

http://www.pudn.com/Download/item/id/1643106.html

[VHDL/FPGA/Verilog] FlashROM

actel fpga fusion kit 使用的flashrom操作
actel fpga fusion kit operation using flashrom (2011-08-31, VHDL, 386KB, 下载31次)

http://www.pudn.com/Download/item/id/1635454.html

[VHDL/FPGA/Verilog] 8b10b

8b10b编解码，aurora协议，遵照xilinx官网文档
8b10b encoder and decoder, aurora protocol (2011-06-28, VHDL, 3KB, 下载62次)

http://www.pudn.com/Download/item/id/1583776.html

[VHDL/FPGA/Verilog] lab2

xilinx官网edk实验，lab2，用nexys 2 板实验源代码
xilinx edk official website experiments, lab2, with nexys 2 plate test source code (2011-05-11, VHDL, 5020KB, 下载9次)

http://www.pudn.com/Download/item/id/1527236.html

[VHDL/FPGA/Verilog] lab1

xilinx官网edk实验，lab1，用nexys 2 板实验源代码
xilinx edk official website experiments, lab1, with nexys 2 plate test source code (2011-05-11, VHDL, 4623KB, 下载4次)

http://www.pudn.com/Download/item/id/1527232.html