与微处理器相连的de10lite板上的设计功能时钟
Design functional clock on de10lite board linked with micro microprocessor (2024-02-21, Tcl, 0KB, 下载0次)
具有参数化宽度的基本3级多周期处理器，遵循Synopsys软件的IC设计流程（Verdi，Design Compiler，Formality，PrimeTime）
Basic 3-stages multicycle processor with parametrized width, following IC Design Flow with Synopsys software (Verdi, Design Compiler, Formality, PrimeTime) (2024-02-16, Tcl, 0KB, 下载0次)
这种简单的设计使用xilinx microblaze处理器来控制xilinx axi uartlite控制器，microblase将uart rx接收的数据写入ddr4ht3（synopsy外部ddr4数据卡）
this simple design use a xilinx microblaze processor to control the xilinx axi_uartlite controller, microblaze will write the data that uart rx received to the ddr4_ht3( synopsy external ddr4 daught card) (2023-12-28, Tcl, 0KB, 下载0次)
基于Python的Kicad sch文件注释器，该注释器按标签类型示意图对元件进行分组
Python based annotator for Kicad sch files, which groups components by label type footprint (2023-11-20, Tcl, 0KB, 下载0次)
在VHDL和Verilog中实现Brainfuck，使用编译器生成匹配的机器代码，
Implementation of Brainfuck in VHDL and Verilog with compiler to generate matching machine code, (2023-10-17, Tcl, 0KB, 下载0次)
这个存储库是我使用Verilog编程之旅的目录。所有工作都是通过Nexys A7 FPGA训练器板和Viv...，
This repository is a catalogue of my programming journey with Verilog. All work was done with the Nexys A7 FPGA Trainer Board and the Vivado Design Suite (2023-09-21, Tcl, 0KB, 下载0次)
Waves是一个简单的时序图编辑器。，
Waves is a simple timing diagram editor., (2023-01-28, Tcl, 0KB, 下载0次)
在开源Skywater 130nm PDK中设计的逆变器布局，
Inverter layout designed in an open-source Skywater 130nm PDK, (2022-03-20, Tcl, 0KB, 下载0次)
使用GF180 Open PDK的基于逆变器的放大器，
Inverter-Based Amplifiers using GF180 Open PDK, (2022-10-28, Tcl, 0KB, 下载0次)
OPENSPARC-T2处理器TFM（SOC设计方法，脚本），
OPENSPARC-T2 Processor TFM (SOC Design methodology, scripts), (2023-04-28, Tcl, 0KB, 下载0次)
synopsys设计编译器使用演示，
synopsys design compiler use demo, (2021-12-17, Tcl, 0KB, 下载0次)
Synopsys DC编译器的典型项目，
Typical project for Synopsys DC Compiler, (2018-06-21, Tcl, 0KB, 下载0次)
Synopsys Design编译器和Synopsys-IC编译器的基本脚本，
Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler, (2018-03-31, Tcl, 0KB, 下载0次)
Synopsys Design编译器、VCS和Tetra MAX，
Synopsys Design compiler, VCS and Tetra-MAX, (2018-05-29, Tcl, 0KB, 下载0次)