验证器验证功能测试,,
verilator verification features tests,, (2023-09-07, SystemVerilog, 0KB, 下载0次)
这在硬件上实现了一个简单的中值滤波器。
This implements a simple median filter on hardware. (2019-08-19, SystemVerilog, 0KB, 下载0次)
基于Fibonacci线性反馈移位寄存器(LFSR)的伪随机数生成
Pseudo random number generation via Fibonacci Linear Feedback Shift Register (LFSR) (2022-12-27, SystemVerilog, 0KB, 下载0次)