DDS波形发生器下载搜索联合开发网

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[VHDL/FPGA/Verilog] GP_top_restored

红外，超声波测距，数码管显示，蜂鸣器，用verilog语言编写
ire，and so on. (2014-07-14, SQL, 1163KB, 下载11次)

http://www.pudn.com/Download/item/id/2587807.html

[VHDL/FPGA/Verilog] _4to2

基于verilog编写的4线2线编码器，在板子上直接运行，相应引脚自己配置
Verilog prepared based 2-wire 4-wire encoders, running directly on the board, the corresponding pin their allocation (2014-04-14, SQL, 1061KB, 下载8次)

http://www.pudn.com/Download/item/id/2510831.html

[VHDL/FPGA/Verilog] Stepper-motor-controller-

步进电机控制器，单机反馈自动控制，vhdl代码。
Stepper motor controller (2011-04-17, SQL, 1KB, 下载23次)

http://www.pudn.com/Download/item/id/1495071.html

[VHDL/FPGA/Verilog] register

用VHDL语言实现各种寄存器，包括简单移位寄存器，并行存取的移位寄存器，算术移位和逻辑移位寄存器
VHDL language using a variety of registers, including a simple shift register, parallel access shift registers, arithmetic and logic shift register shift (2011-04-05, SQL, 1581KB, 下载6次)

http://www.pudn.com/Download/item/id/1479596.html

[VHDL/FPGA/Verilog] DDS

直接数字信号源的源代码和发生器的设计报告
Direct digital signal source code and design report (2010-03-20, SQL, 197KB, 下载13次)

http://www.pudn.com/Download/item/id/1093923.html

[VHDL/FPGA/Verilog] MyFilter

FPGA实现数字滤波器，用VHDL语言实现的直接1型FIR滤波器，具有较好的参考价值。
FPGA realization of digital filters using VHDL language to achieve the direct FIR filter type 1, has a good reference value. (2009-08-19, SQL, 2KB, 下载45次)

http://www.pudn.com/Download/item/id/882726.html

[VHDL/FPGA/Verilog] cnt10

基于vhdl的10进制计数器模块，实现0-9计数
VHDL-based 10-band counter module, to achieve 0-9 count (2008-01-01, SQL, 23KB, 下载7次)

http://www.pudn.com/Download/item/id/386287.html

[VHDL/FPGA/Verilog] cnt6

基于vhdl的6进制计数器模块，实现0-5计数
VHDL-based 6-band counter module, to achieve 0-5 count (2008-01-01, SQL, 22KB, 下载3次)

http://www.pudn.com/Download/item/id/386286.html

总计:8