[GDI/图象编程] lecture3_VHDL

组合逻辑设计 时序逻辑设计 状态机等的vhdl语言设计原理与解说（包括一些基本的加法 计数 移位器 状态机等）
Combinational logic design sequential logic design, such as state machine design principle of the VHDL language and explanations (including some basic adder count shifter state machine, etc.) (2008-06-17, PPT, 326KB, 下载6次)