UART的USB ip核vhdl实现， 包括发送机， 接收机， 控制器， 初始模块， 以及各模块的package
USB_UART implementation on FPGA board, including transmitter, receivre, controller, initialization, and package (2018-05-06, VHDL, 1122KB, 下载0次)
基于USB接口的边界扫描测试控制器设计,很实用，值得参考。
jtag tap controller (2016-02-24, VHDL, 375KB, 下载1次)
USB2.0控制器源码,硬件实现USB2.0控制器
USB2.0 controller source code, hardware realization of USB2.0 controller (2009-07-14, VHDL, 204KB, 下载6次)
UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。
UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features. (2009-06-02, VHDL, 206KB, 下载83次)