基于VHDL 实现1小时的数字跑表，包含计数器、数据存储等部分
VHDL realization of digital stopwatch based on 1 hours, including counter, data storage etc. (2018-04-08, VHDL, 15KB, 下载1次)
数字钟的verilog实现程序。包含各个模块。分别为顶层模块，小时计数器，分计数器，秒计数器等。
Digital clock verilog implementation process. With each module. Were top-level module, hours counter, minutes counter, second counter and so on. (2010-03-24, VHDL, 341KB, 下载10次)
本设计是用32位的并行全加器的,可以实现浮点运算!
The design is a parallel 32-bit full adder, and floating-point operations can be achieved! (2009-05-27, VHDL, 272KB, 下载8次)
（1）S2S1=00时，实现模3计数，触发器的状态一次0→1→2→0；
（2）S2S1=01时，实现模5计数，触发器的状态一次0→1→2→3→4→0；
(3) S2S1=10时，实现模7计数，触发器的状态一次0→1→2→3→4→5→6→0；
(4) S2S1=11时，实现模7计数，触发器的状态一次0→1→2→3→4→5→6→7→0
Variable modulus counter (2009-05-19, VHDL, 23KB, 下载1次)
简单的38译码器,语句较为简捷明了.供大家参考学习.
Simple decoder 38, a more simple and clear statement. Learning for your reference. (2009-04-29, VHDL, 41KB, 下载1次)
闪存芯片编程,应用于从只读存储器引导系统
Intel Flash chip i28f160,i28f320 programing (2009-02-19, VHDL, 5KB, 下载1次)
基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真
CPLD-based counters realize optical ranging, single-chip microcomputer that contains timing control and realize the adoption of Verilog simulation (2008-08-19, VHDL, 2KB, 下载17次)
非常有参考价值的 计数器 源代码，用到了许多的编写程序的技巧，可以借鉴
Very useful counter source code, used in many programming skills, can learn from (2008-07-24, VHDL, 83KB, 下载119次)
8位移位寄存器，当高电平来时移入下一位！
8-bit shift register, when the high level when the next move! (2008-05-16, VHDL, 19KB, 下载17次)