该项目的目标是在Zybo上构建一个vga视频模式生成器，并通过在zynq上运行的嵌入式linux操作系统来控制它。，
The aim of the project is to build a vga video pattern generator on Zybo and control it by an embedded linux OS running on the zynq., (2017-07-24, VHDL, 0KB, 下载0次)
VHDL实现4选1数据选择器
entity mux41a is
port(a,b:in std_logic;
s1,s2,s3,s4:in std_logic;
y: out std_logic);
end entity mux41a;
VHDL implementation of one out of four data selector (2020-05-18, VHDL, 2KB, 下载0次)
使用verilog语言实现了UDP协议网络通信
Verilog protocol is used to realize UDP protocol network communication (2017-08-18, VHDL, 636KB, 下载109次)
嵌入式处理器 OR2000的源代码，适合有一定基础的人学习
Embedded processor OR2000 source code, suitable for a certain person based learning (2015-01-02, VHDL, 181KB, 下载13次)
ARM学习规划
[table][tr][td]本帖隐藏的内容需要回复才可以浏览（现在不用回复了）
ARM+LINUX路线，主攻嵌入式Linux操作系统及其上应用软件开发目标：
（1） 掌握主流嵌入式微处理器的结构与原理（初步定为arm9）
（2） 必须掌握一个嵌入式操作系统 （初步定为uclinux或linux,版本待定）
（3） 必须熟悉嵌入式软件开发流程并至少做一个嵌入式软件项目。
ARM learning plan [table] [tr] [td] The Hidden content need to respond before they can view (now do not have responded) ARM+ LINUX line, the main embedded Linux operating system and application software on the development objectives: (1) master the mainstream structure and principle of the embedded microprocessor (initially arm9) (2) must master an embedded operating system (initially uclinux or linux, version to be determined) (3) must be familiar with embedded software development process and at least to do an embedded software project. (2011-09-23, VHDL, 7KB, 下载4次)
DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。
DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter. (2010-01-25, VHDL, 43KB, 下载43次)