FPGA实现3-8译码器用于实验测试，非常适合于初学者
FPGA implementation decoder (2018-02-12, VHDL, 157KB, 下载1次)
adc寄存器配置，功能代码编写，实现1GSPS采样率信号采集功能
ADC register configuration (2017-07-20, VHDL, 148KB, 下载1次)
实现信号的分频，并且波形设计完整，无毛刺，可以运用与信号的检测，放大。
Implement signal frequency, and waveform design complete, no glitches, can use the detection signal amplification. (2015-08-14, VHDL, 2888KB, 下载3次)
用于全国大学生电子设计大赛，一个基于c8051f120的函数信号发生器
For National Undergraduate Electronic Design Contest, a function of the signal generator based on c8051f120 (2013-09-23, VHDL, 54KB, 下载1次)
1、 了解开发平台中触摸屏控制器的基本结构。
2、 熟悉平台中触摸屏控制器的工作原理。
3、 了解ADS7843的工作原理。
4、 掌握如何使用触摸屏控制器读取触摸板上的坐标信息。
1, to understand the development platform of the basic structure of the touch screen controller. 2, familiar platform touchscreen controller works. 3, to understand ADS7843 works. 4, learn how to use the touch screen controller reads the coordinate information on the TouchPad. (2013-05-22, VHDL, 2145KB, 下载3次)
篮球计分器，包含篮球赛计时，加一分三分，暂停，24秒等
Basketball scoring, contains basketball game timing, plus one-third of pause, 24 seconds (2012-10-10, VHDL, 1197KB, 下载27次)
在ISE中用DDS核产生sin函数 可用于信号源的产生、信号的调制等等
generating sin function using IP CORE DDS in ISE (2011-06-10, VHDL, 1KB, 下载19次)
DS18B20传感器，汇编语言，处理闪烁现象
DS18B20 sensors, assembly language, processing flicker (2011-04-23, VHDL, 7KB, 下载3次)
用80c51制作八路抢答器的汇编语言程序设计
Produced by eight Responder 80c51 assembly language programming (2011-04-23, VHDL, 4KB, 下载3次)
西门子PLC程序例子集合包括PID调节、机械手、数码显示、变频器正反转、交通灯、喷泉、温度控制、三相步进电机
Siemens PLC program example set includes PID regulation, robot, digital display, reversing the drive, traffic lights, fountains, temperature control, three-phase stepper motor (2011-04-12, VHDL, 78KB, 下载311次)
CORDIC算法要求：CORDIC算法的代码，写成一个模块，有输入输出、原理、步骤、结果，有仿真波形
CORDIC algorithm requires: CORDIC algorithm code, written in a module, there are input and output, principles, procedures, results, a simulation waveform (2011-03-08, VHDL, 69KB, 下载56次)
用NIOSII生成的VGA显示程序,可以在显示器上显示通讯内容
用NIOSII生成的VGA显示程序,可以在显示器上显示通讯内容 (2009-10-12, VHDL, 575KB, 下载27次)
出租车自动计价器设计
要求：
计一个出租车计价器。
该计价器的计费系统：行程 3公里内，且等待累计时间2分钟内，起步费为10元；3公里外以每公里1.6元计费，等待累计时间2分钟外以每分钟以1.5元计费。
并能显示行驶公里数、等待累计时间、总费用。
Taxi automatic meter design requirements: 1 meter taxi meter. The meter' s billing system: stroke within 3 km, and the total waiting time of 2 minutes, the starting fee is 10 yuan 3 kilometers away, charging 1.6 yuan per kilometer, waiting outside the aggregate time of 2 minutes to 1.5 yuan per minute billing. And can show the number of road miles, waiting for the accumulated time, the total cost. (2009-09-24, VHDL, 53KB, 下载35次)
自动升降电梯控制器设计
要求：
设计一个6层楼的电梯控制器。
该控制器可控制电梯完成6层楼的载客服而且遵循方向优先原则，并能响应提前关门延时关门，并具有超载报警和故障报警；
同时指示电梯运行情况和电梯内外请求信息。
Auto-Lift elevator controller design requirements: design of a six-story elevator controller. The controller can control the completion of six-story elevator containing the principle of giving priority customer service, and follow the directions, and can respond to close ahead of schedule delay closing, and has overload alarm and fault alarm also instructed the elevator and elevator operation request information both inside and outside. (2009-09-24, VHDL, 138KB, 下载15次)
Xilinx公司的 i2c总线驱动器 VHDL程序
Xilinx i2c bus driver VHDL procedures (2009-06-11, VHDL, 692KB, 下载80次)
能够产生方波、三角波、正弦波、及阶梯波，并且可以通过选择开关选择相应的频率输出和波形输出；通过按键确定输出的波形及确定是否输出波形.
Able to generate square wave, triangle wave, sine wave, and wave ladder, and can select the appropriate choice of switching frequency output and the waveform output through the keys to determine the output waveform and to determine whether the output waveform. (2009-02-10, VHDL, 408KB, 下载22次)
程序提供了一种2选1选择器的算法，只需稍加即可改成n选1选择器。哇！
Program provides a 2 election 1 selector algorithm, just a little can be changed to n choose 1 selector. Wow! (2008-10-18, VHDL, 125KB, 下载4次)
基于DDS的数字移相正弦信号发生器设计，EDA技术在全国大学生电子设计竞赛中的应用
DDS-based digital phase-shifting sinusoidal signal generator design, EDA Technology in the National Undergraduate Electronic Design Contest Application (2008-06-19, VHDL, 217KB, 下载247次)
只要或上有事件发生，门实例语句即被执行。只要或上有事件发生，就执行语句，并且只要或上有事件发生，就执行连续赋值语句。
Or as long as there are incidents, the door was the implementation of example sentences. Or as long as there are incidents on the implementation of statements, and as long as or incidents on the implementation of continuous assignment statements. (2008-06-10, VHDL, 1KB, 下载33次)
一个QEP电路的verilog代码。输入信号是光电编码器的A相和B相信号和一个处理时钟，输出的是计数信号和方向信号。
A QEP circuit Verilog code. Input signal is the optical encoder of the A phase and B and believe that a deal with the clock, the output is the count signal and direction signal. (2008-05-03, VHDL, 1KB, 下载250次)