fpga平台实现srio通信,以及srio端口寄存器设计。
FPGA platform to achieve sRIO communication, as well as sRIO port register design. (2017-07-09, VHDL, 2145KB, 下载50次)
32位寄存器的VHDL的原代码下载,COOLCOOLCOOL
32-bit register of the original VHDL code download, COOLCOOLCOOL (2008-08-09, VHDL, 3KB, 下载27次)
里面是一个FIR滤波器的VHDL语言 具体的功能里面有详细的介绍 对毕业设计者很有帮助的
There is a FIR filter VHDL language specific features which are detailed introduction to the graduate designers helpful (2008-04-15, VHDL, 4KB, 下载160次)