[图形图象] SVG-control--system
提出一种控制静止无功发生器（SVG）输出电流的策略，既能实时补偿负荷无功，又能改善负荷接入电
网点的电压波形。
Proposed a controlled static var generator (SVG) output current strategy, both real-time compensation of reactive power load, but also improve the load connected to the grid voltage waveform points. (2014-04-09, VHDL, 308KB, 下载9次)
[图形图象] VHDL-VERILOG_HDL
基于FPGA的视频图像采集系统的设计与实现的 ＣＣＤ 图像传 感器采集图像， 经 ＤＳＰ 处理后输出的 ＰＡＬ 制 数字视频信
FPGA based video image acquisition system design and implementation of the CCD image sensor sensor image acquisition, after the treatment by DSP output PAL for digital video. (2012-05-19, VHDL, 12KB, 下载9次)
[图形图象] vga
产生缩进和扩张的彩环,在收缩和扩张时，彩环的颜色也在不断地发生变化，适合于VGA实验。
Production and expansion of the color ring indent (2010-06-02, VHDL, 1KB, 下载8次)
[图形图象] wb_dma
wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发
dma controller with wishbone interface，fitting for soc design，especially for video development. (2009-09-15, VHDL, 140KB, 下载22次)
[图形图象] VGA
基于CPLD的VGA控制器的实现，600*800 72Hz
CPLD based on the realization of the VGA controller, 600* 800 72Hz (2009-06-30, VHDL, 306KB, 下载8次)
[图形图象] ImageProcessing
应用不同的用户可选择回旋滤波器的图像处理部件。一套PC应用程序将图像档案下载到一个FPGA可访问的存储器阵列。处理过的图像显示在连接的VGA显示屏上。
Users can choose to apply a different room of the image processing filter components. A set of PC applications will be image files downloaded to a FPGA can access the memory array. Processed image displayed on the VGA display connection. (2009-05-25, VHDL, 15045KB, 下载54次)
[图形图象] VGA_change
程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例，源文件保存在src目录，QII的工程文件保存在Proj目录。
Program can display in VGA resolution display to 800x600 square sample and letters examples, source files stored in the src directory, QII the project file stored in the directory Proj. (2009-01-06, VHDL, 2646KB, 下载7次)
[图形图象] fqdivider
数字积分dda直线插补器
希望与数控系统设计的朋友一起学习进步
The number of points straight dda Interpolator hope and numerical control system designed to study the progress of friends (2008-06-20, VHDL, 154KB, 下载78次)
[图形图象] count
EDA实验--利用宏功能模块实现的计数器: 利用-MegaWizard Plug-In Manager创建一个16位计数器，具备正逆计数以及预置，清0功能。本实验由RESET健清0，PSW1健控制预制数，按下置入1234，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值，编辑源程序，观察实验结果。
EDA experiments using macro function modules realize the counter: use-MegaWizard Plug-In Manager to create a 16-bit counter, with counting and the inverse is preset, the Qing 0 function. The experiment was conducted by RESET Kin-ching 0, PSW1 prefabricated Kin control number, pressed into 1234, PSW2 control is against the count, press the reduced count, count up positive. The use of VGA as output device, shows the value, edit the source code to observe the experiment results. (2008-06-01, VHDL, 2KB, 下载10次)
[图形图象] lift
4层电梯控制器（单向层层停控制方式）VHDL源程序(绝对通，符详细注释)
4-storey elevator controller (one-way stop control at each level) VHDL source code (absolute Tong, Fu detailed notes) (2008-04-12, VHDL, 8KB, 下载127次)