针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design
Compile所用的环境和脚本。
The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. (2014-01-08, VHDL, 34KB, 下载17次)
UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。
UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allows for full-duplex serial link communications. (2008-11-29, VHDL, 5KB, 下载19次)
伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。
Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code. (2008-11-12, VHDL, 1KB, 下载356次)
这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.
This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz. (2008-11-11, VHDL, 290KB, 下载104次)
CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset
CRC code generator and calibration program Features: Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset (2008-09-11, VHDL, 5KB, 下载30次)