为实现基于 FPGA 的 DDS数字调幅波,提出以调整调制指数控制字与频率控制字,通
过查表得到所需数字序列的思想与方法, MATLAB6. 5仿真与样机实验表明该方法是行之有效的 。
To generate digita l DDS AM by FPGA, the idea and m ethod to achieve dig it sequence
w ere presen ted by looking up the table w ith the he lp of ad justing index modula tion control wo rd.
MATLAB6. 5 si m ula tion and sam p le m achine experi m en t show ed thism e thod w as effective (2020-03-10, VHDL, 1145KB, 下载1次)
用来测量正弦信号、矩形信号、三角形信号等波形工作频率的仪器
Instrument for measuring the working frequency of sinusoidal, rectangular and triangular waveforms (2019-05-18, VHDL, 3328KB, 下载2次)
基于vhdl语言的DDS波形发生器及其2fsk调制器的实现
DDS waveform generator based on VHDL language and Realization of its 2FSK modulator (2018-12-16, VHDL, 481KB, 下载0次)
实现占空比50%的五分频电路模块设计，实现奇数分频：
1、当NRESET=0的时候，数据复位（清零） 、奇数分频，输出波形稳定后，实现奇数分频功能 3、50%占空比，输出波形稳定后，分频后的时钟“1”的“0”占信号周期各50% 注意：刚开始分频的数据可能不对，结果只取稳定输出后的信号
A five frequency division circuit with duty ratio of 50% (2018-10-17, VHDL, 18KB, 下载0次)
cnt10,cnt24,cnt60,decoder,50Mhzdiv1hz wrriten in verilog language
cnt10,cnt24,cnt60,decoder,50Mhzdiv1hz wrriten in verilog language (2018-05-28, VHDL, 2KB, 下载0次)
基于VHDL卷积交织器的设计与实现(1)
Design and implementation of convolution Interleaver Based on VHDL (2017-12-27, VHDL, 209KB, 下载4次)
本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。
The stopwatch timer is used in sports competitions and in various fields where requirements are more accurate. This timer is written in a VHDL language using a dedicated chip. In addition to switching, clocking and display functions, it also includes 1/100s timers, all control and timing functions, which are small in size and easy to carry. (2017-06-12, VHDL, 3KB, 下载3次)
实现定时器功能，分别有秒针，分钟，小时，到一天后led灯闪烁一下。
To achieve timer function, respectively, seconds, minutes, hours, to one day look after the led light flashes. (2010-02-01, VHDL, 1KB, 下载2次)
在EDA开发中编程达到乐曲播放功能，使用层次化设计方法，实现乐曲发生器的设计。
In the EDA development program to music playback, the use of hierarchical design methodology to achieve music generator design. (2009-10-12, VHDL, 35KB, 下载2次)
关于DDR2 SDRAM 控制器的相关论文资料
ddr2_sdram_controller (2009-08-21, VHDL, 5542KB, 下载11次)
用状态机实现序列检测器的设计，并采用ROM结构输入待测序列进行仿真测试。
sequence inspector (2009-07-04, VHDL, 455KB, 下载4次)
含计数使能、异步复位和计数值并行预置功能4位加法计数器
EDA Electronics Design Automation (2009-05-20, VHDL, 270KB, 下载2次)
一种基于turbo码的交织器设计，运用vhdl语言。
something about turbo。 (2009-04-23, VHDL, 115KB, 下载10次)
介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。
Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules of the design method and device using VHDL and FPGA implementation of IIR digital filter. (2009-03-06, VHDL, 646KB, 下载218次)
乐曲发生器，可以用FPGA通过BUZZER生成音乐
music buzzer (2009-02-18, VHDL, 53KB, 下载4次)
60进制计数器 序列检测器
适用于MAX PLUS2程序开发
60 hexadecimal counter sequence detector for MAX PLUS2 development (2009-01-05, VHDL, 1KB, 下载9次)
双向可控移位寄存器及存储器设计实验 双向可控移位寄存器及存储器设计实验 (2008-07-08, VHDL, 29KB, 下载10次)
http://www.pudn.com/Download/item/id/506365.html
线性相位FIR滤波器（17阶）的VHDL语言设计
功能很强大，很好用
Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use (2008-06-26, VHDL, 145KB, 下载89次)
时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件
Clock Generator clkgen use of external clock signal clk to generate a series of clock signal clk1, fetch, alu_clk sent to other parts of the CPU (2008-05-07, VHDL, 1KB, 下载12次)
本论文是基于FPGA的多功能信号发生器，其中包括了整个设计流程
This paper is based on the multi-function signal generator of the FPGA, including the entire design flow (2008-05-07, VHDL, 77KB, 下载102次)