[汇编语言] sy3
?交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；
?当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；
Primary description of running water lamp (2019-12-18, VHDL, 4325KB, 下载1次)
[汇编语言] qdaqi
8路抢答器 整套代码已经验证可以使用 淘宝付费购买来的 免费分享
Based on the FPGA grab answering device, which contains various features, Taobao paid to buy, is now free to share (2018-11-21, VHDL, 303KB, 下载0次)
[汇编语言] MorseaYima
使用汇编语言编写的摩斯电码发生器与译码器，可以通过用户输入完成摩斯码的生成与翻译
Written in assembly language using Morse code generator and decoder, Morse code generation can be done through the user input and Translation (2014-02-24, VHDL, 2KB, 下载5次)
[汇编语言] bjq7
七人表决器，7个人中至少4个人表示同意才回选择通过
Seven voting (2013-03-15, VHDL, 40KB, 下载3次)
[汇编语言] LED
具有产生三种基本波形脉冲信号（正弦波、矩形波和三角波），以及三次（及三次以下）谐波与基波的线性组合脉冲波形输出，且单脉冲输出脉宽及连续脉冲输出频率可调，范围从100HZ到1kHZ,步进为100HZ；幅度可调，从0到5伏，步进为0.1V
failed to translate (2012-05-06, VHDL, 3KB, 下载7次)
[汇编语言] niub.rar
正弦函数表的设计做正弦波发生器的也许能用到
Design of the sine function table can be used to do, perhaps, to the sine wave generator (2011-04-22, VHDL, 3KB, 下载2次)
[汇编语言] 7renbiaojueqi
VHDL实现的一个七人表决器源程序，当人数多于四人时表决通过
VHDL implementation of a seven-member voting machine source code, when the number of people vote more than four hours (2009-12-07, VHDL, 216KB, 下载9次)
[汇编语言] pwm10
產生三角波來比較pwn輸入訊號,以此產生pwm之波形始需要的硬體設備驅動
Triangular wave generated to compare the input signal pwn as the pwm waveforms generated only need the hardware device driver (2009-07-30, VHDL, 1KB, 下载1次)
[汇编语言] sheji
用数码管显示自己的学号，用ip核显示波形，配合matalab
Digital display its own study, using nuclear show ip waveform with matalab (2009-07-02, VHDL, 672KB, 下载3次)
[汇编语言] jishuqi
在用VHDL语言描述一个计数器时，如果使用了程序包ieee.std_logic_unsigned，则在描述计数器时就可以使用其中的函数“+”（递增计数）和“-”（递减计数）。假定设计对象是增1计数器并且计数器被说明为向量，则当所有位均为‘1’时，计数器的下一状态将自动变成‘0’。举例来说，假定计数器的值到达“111”是将停止，则在增1之前必须测试计数器的值。
如果计数器被说明为整数类型，则必须有上限值测试。否则，在计数顺值等于7，并且要执行增1操作时，模拟器将指出此时有错误发生
VHDL language used to describe a counter, if used the package ieee.std_logic_unsigned, counters in the description of which can be used when the function "+" (count increments) and "-" (decrease count). By the assumption that the design is a counter and that counter was for the vector, then when all the spaces are' 1 ' , the counter will automatically become the next state' 0' . For example, assume that the value of counter to " 111" is to stop, then prior to the test by a counter value. If the counter has been that an integer type, there must be limits on testing. Otherwise, the count value of 7-shun, and to be implemented by 1 operation, at this time simulator will be pointed out that an error occurred (2009-05-31, VHDL, 29KB, 下载1次)
[汇编语言] developmentofA_Dconverter
a/d转换器和d/a转换器的发展动态！写论文可能用到。
a/d converters and d/a converter developments! May be used to write papers. (2009-04-29, VHDL, 244KB, 下载2次)
[汇编语言] m
M序列的源代码，用于基带信号发生器的设计
M series source code for the base-band signal generator design (2009-04-05, VHDL, 11KB, 下载62次)
[汇编语言] full_adder
八位全加器，实现自动加法，哈哈哈，大家共享
hello (2009-03-26, VHDL, 204KB, 下载2次)
[汇编语言] 1234
多功能数字钟，、在quartus 2环境中编译通过；
4、仿真通过并得到正确的波形；
5、给出相应的设计报告
Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report (2008-12-25, VHDL, 1160KB, 下载59次)
[汇编语言] sync_vhdl
产生复合同步信号波形，可适用QUARTUS来运行并查看波形
Generate composite sync signal waveform, the applicable Quartus to run and view the waveform (2008-10-30, VHDL, 1KB, 下载13次)
[汇编语言] compelete
三层电梯 十分有用哦 无须改正,只要输入,通过防真就能得到答案.
Elevator very useful three-oh there is no need to correct, as long as the input, through the anti-real will be able to get an answer. (2008-10-29, VHDL, 5KB, 下载100次)
[汇编语言] compare_4
4位比较器，通过vhdl语言实现的四位比较器
4 comparator, through the VHDL language realize the four comparator (2008-07-14, VHDL, 2KB, 下载20次)
[汇编语言] VHDLsiweiquanjiaqqi
这是一个利用MAX PULL 制作的VHDL的四位全加器的程序 如果有需要仿真图的 请叫站长联系我
This is a MAX PULL using VHDL produced four full-adder process simulation map, if necessary please contact me call station (2008-06-14, VHDL, 1KB, 下载4次)
[汇编语言] 11
用1位半减器构成一位全减器，之后再构成8位全减器。有三个组件：h_suber，一位半减器，f_suber，一位全减器，f_suber8，8位全减器。
With a half-wide device constituted by a browser, and then pose a 8-wide by browser. Has three components: h_suber, a half device, f_suber, a full-cut device, f_suber8, 8 are all by browser. (2008-05-21, VHDL, 1KB, 下载25次)
[汇编语言] PWM
利用汇编语言编写,VHDL,实现PWM波形转换电压,直接导入单片机即可运行,产生波形输出实现转换电压的功能.
Prepared to use assembly language, VHDL, realize PWM waveform converter voltage, can be run directly into single-chip, resulting in the output waveform realize the function of voltage conversion. (2008-04-20, VHDL, 1040KB, 下载25次)